公开(公告)号：US08861264B2

公开(公告)日：2014-10-14

申请号：US13178993

申请日：2011-07-08

申请人： Ick Hyun Song ,  Ki Whan Song ,  Jin-Young Kim

发明人： Ick Hyun Song ,  Ki Whan Song ,  Jin-Young Kim

IPC分类号： G11C11/00 ,  G11C13/00 ,  G11C8/08 ,  G11C7/12

CPC分类号： G11C7/12 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/004

摘要： A pre-charge controlling method and device are provided. The pre-charge controlling method includes pre-charging a first global bit line with a first pre-charge voltage by using at least a first pre-charge circuit located between a plurality of sub arrays included in a memory cell array and pre-charging the first global bit line with a second pre-charge voltage by using a second pre-charge circuit located outside the memory cell array.

摘要翻译： 提供了一种预充电控制方法和装置。 预充电控制方法包括通过使用位于存储单元阵列中包括的多个子阵列之间的至少第一预充电电路来对具有第一预充电电压的第一全局位线进行预充电，并对 通过使用位于存储单元阵列外部的第二预充电电路，具有第二预充电电压的第一全局位线。

公开(公告)号：US08199592B2

公开(公告)日：2012-06-12

申请号：US12591196

申请日：2009-11-12

申请人： Jin-Young Kim ,  Chul-Woo Park ,  Ki-Whan Song

发明人： Jin-Young Kim ,  Chul-Woo Park ,  Ki-Whan Song

IPC分类号： G11C7/00

CPC分类号： G11C11/4099 ,  G11C11/4091

摘要： A semiconductor memory device having the mismatch cell makes a capacitance difference between a bit line pair relatively large during a read operation using at least one dummy memory cell as a mismatch cell selected together with a corresponding memory cell. Therefore, data of a semiconductor memory device may be detected more easily.

摘要翻译： 具有不匹配单元的半导体存储器件在使用至少一个虚拟存储器单元作为与对应的存储器单元一起选择的不匹配单元的读取操作期间，位线对之间的电容差相对较大。 因此，可以更容易地检测半导体存储器件的数据。

公开(公告)号：US20110305069A1

公开(公告)日：2011-12-15

申请号：US13155492

申请日：2011-06-08

申请人： Jin-Young Kim ,  Ki-Whan Song

发明人： Jin-Young Kim ,  Ki-Whan Song

IPC分类号： G11C11/00

CPC分类号： G11C5/063 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038

摘要： A nonvolatile memory device includes: a memory array including a plurality of memory banks which are arranged in a first direction; a write global bit line and a read global bit line extending in the first direction to be shared by the memory banks; a write circuit connected to the write global bit line and disposed on a first side of the memory array; and a read circuit connected to the read global bit line and disposed on a second side of the memory array opposite the first side of the memory array, wherein each of the memory banks extends in a second direction different from the first direction and comprises a plurality of nonvolatile memory cells, each of the nonvolatile memory cells having a variable resistive element whose resistance value varies according to data stored therein.

摘要翻译： 非易失性存储器件包括：存储器阵列，包括沿第一方向布置的多个存储体; 写入全局位线和在第一方向上延伸以由存储体共享的读取全局位线; 写入电路，连接到写入全局位线并且设置在存储器阵列的第一侧上; 以及读取电路，连接到读取的全局位线并且设置在与存储器阵列的第一侧相对的存储器阵列的第二侧上，其中每个存储体沿与第一方向不同的第二方向延伸并且包括多个 的非易失性存储单元，每个非易失性存储单元具有可变电阻元件，其电阻值根据存储在其中的数据而变化。

公开(公告)号：US20100124135A1

公开(公告)日：2010-05-20

申请号：US12591254

申请日：2009-11-13

申请人： Jin-Young Kim ,  Ki-Whan Song

发明人： Jin-Young Kim ,  Ki-Whan Song

IPC分类号： G11C16/06

CPC分类号： G11C11/4091 ,  G11C11/4097 ,  G11C2207/002

摘要： The semiconductor memory device includes a memory cell array and a switching circuit. The memory cell array includes a plurality of first memory cells connected between word lines and first local bit lines, and a plurality of second memory cells connected between the word lines and second local bit lines. The switching circuit is configured to respectively connect the first local bit lines to first global bit lines during a first sensing period, and to respectively connect the second local bit lines to second global bit lines during a second sensing period of a reading operation. The semiconductor memory device further includes a sensing circuit configured to sense and amplify data from the first global bit lines during the first sensing period, and to sense and amplify data from the second global bit lines during the second sensing period of the reading operation.

摘要翻译： 半导体存储器件包括存储单元阵列和开关电路。 存储单元阵列包括连接在字线和第一局部位线之间的多个第一存储单元，以及连接在字线和第二局部位线之间的多个第二存储单元。 开关电路被配置为在第一感测周期期间将第一本地位线分别连接到第一全局位线，并且在读取操作的第二感测周期期间将第二局部位线分别连接到第二全局位线。 半导体存储器件还包括感测电路，其被配置为在第一感测周期期间感测和放大来自第一全局位线的数据，并且在读取操作的第二感测周期期间感测和放大来自第二全局位线的数据。

公开(公告)号：US20080151665A1

公开(公告)日：2008-06-26

申请号：US11882931

申请日：2007-08-07

申请人： Jin-Young Kim ,  Ki-Whan Song ,  Duk-Ha Park

发明人： Jin-Young Kim ,  Ki-Whan Song ,  Duk-Ha Park

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C11/4096 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2211/4016

摘要： One embodiment includes a plurality of word lines, a plurality of bit lines intersecting with the plurality of word lines, a plurality of memory cells formed at intersections of and connected to the plurality of word lines and the plurality of bit lines. Each of the plurality of memory cells may be a floating body cell. A bit line selecting circuit may be configured to selectively connect each of the plurality of bit lines to an output bit line. The embodiment may further include plurality of sense amplifiers, where the plurality of sense amplifiers is greater than one and less than the plurality of bit lines in number. A sense amplifier switching structure may be configured to selectively connect each of the plurality of sense amplifiers to the output bit line.

摘要翻译： 一个实施例包括多个字线，与多个字线相交的多个位线，多个存储单元，形成在多个字线和多个位线的交叉点处并与之连接。 多个存储单元中的每一个可以是浮动体单元。 位线选择电路可以被配置为选择性地将多个位线中的每一个连接到输出位线。 该实施例还可以包括多个读出放大器，其中多个读出放大器的数量大于一个且小于多个位线。 读出放大器切换结构可以被配置为选择性地将多个读出放大器中的每一个连接到输出位线。

公开(公告)号：US20070252196A1

公开(公告)日：2007-11-01

申请号：US11801915

申请日：2007-02-08

申请人： Jin-Young Kim ,  Ki-Whan Song

发明人： Jin-Young Kim ,  Ki-Whan Song

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L31/00 ,  H01L29/94

CPC分类号： H01L21/823842 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052

摘要： A semiconductor device is provided which includes an NMOS vertical channel transistor located on a substrate and including a p+ polysilicon gate electrode surrounding a vertical p-channel region, and a PMOS vertical channel transistor located on the substrate and including an n+ polysilicon gate electrode surrounding a vertical n-channel region. The NMOS and PMOS vertical channel transistors are optionally operable in a CMOS operational mode.

摘要翻译： 提供了一种半导体器件，其包括位于衬底上并包括围绕垂直p沟道区的p +多晶硅栅电极的NMOS垂直沟道晶体管和位于衬底上的PMOS垂直沟道晶体管，并且包括n + 垂直n沟道区域。 NMOS和PMOS垂直沟道晶体管可选地以CMOS操作模式工作。

公开(公告)号：US07944759B2

公开(公告)日：2011-05-17

申请号：US12285520

申请日：2008-10-08

申请人： Jin-Young Kim ,  Ki-Whan Song

发明人： Jin-Young Kim ,  Ki-Whan Song

IPC分类号： G11C16/04

CPC分类号： G11C5/147 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2211/4016

摘要： A semiconductor memory device includes a memory cell array including a plurality of memory cells having a transistor with a floating body, a source line driver configured to control the source lines to select the memory cells in response to an address signal, a source line voltage generation unit configured to generate a source line target voltage, receive an source line output voltage from the source line driver, compare the level of the source line output voltage with the level of the source line target voltage, generate a source line voltage of which the level is adaptively varied according to a temperature, and a sense amplifier configured to sense a difference in current flowing through the bit lines in response to data read from a selected memory cell, amplify the difference to a level having high output driving capability and output the amplified current.

摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列包括具有浮置体的晶体管的多个存储器单元，源极线驱动器，被配置为响应于地址信号控制源极线选择存储单元，源极线电压产生 被配置为产生源极线路目标电压的单元，从源极线驱动器接收源极线路输出电压，将源极线路输出电压的电平与源极线路目标电压的电平进行比较，生成源极线电压， 根据温度自适应地变化;以及读出放大器，被配置为响应于从选择的存储单元读取的数据来感测流过位线的电流差，将该差放大到具有高输出驱动能力的电平，并输出放大的 当前。

公开(公告)号：US07843750B2

公开(公告)日：2010-11-30

申请号：US11797867

申请日：2007-05-08

申请人： Duk-Ha Park ,  Ki-Whan Song ,  Jin-Young Kim

发明人： Duk-Ha Park ,  Ki-Whan Song ,  Jin-Young Kim

IPC分类号： G11C7/00

CPC分类号： H01L27/10876 ,  G11C7/1042 ,  G11C7/12 ,  G11C11/404 ,  G11C11/4094 ,  H01L29/78 ,  H01L29/7827

摘要： A semiconductor memory device including a transistor having a vertical channel structure is provided. The device includes a first sub memory cell array including a first memory cell connected to a first bit lines and including a transistor having a vertical channel structure, a second sub memory cell array including a second memory cell connected to a first inverted bit lines and including a transistor having a vertical channel structure, and a plurality of precharge blocks. In addition, first and second precharge blocks are disposed at first and second sides of the first bit line and precharge the first bit line, and third and fourth precharge blocks are disposed at first and second sides of the first inverted bit line and precharge the first inverted bit line.

摘要翻译： 提供一种包括具有垂直沟道结构的晶体管的半导体存储器件。 该器件包括第一子存储单元阵列，该第一子存储单元阵列包括连接到第一位线并包括具有垂直沟道结构的晶体管的第一存储单元，第二子存储单元阵列，包括连接到第一反相位线的第二存储单元， 具有垂直沟道结构的晶体管和多个预充电块。 此外，第一和第二预充电块设置在第一位线的第一和第二侧并对第一位线进行预充电，并且第三和第四预充电块设置在第一反相位线的第一和第二侧，并且对第一 反转位线。

公开(公告)号：US08503218B2

公开(公告)日：2013-08-06

申请号：US13155492

申请日：2011-06-08

申请人： Jin-Young Kim ,  Ki-Whan Song

发明人： Jin-Young Kim ,  Ki-Whan Song

IPC分类号： G11C11/00 ,  G11C5/06 ,  G11C11/06 ,  G11C7/10

CPC分类号： G11C5/063 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038

摘要： A nonvolatile memory device includes: a memory array including a plurality of memory banks which are arranged in a first direction; a write global bit line and a read global bit line extending in the first direction to be shared by the memory banks; a write circuit connected to the write global bit line and disposed on a first side of the memory array; and a read circuit connected to the read global bit line and disposed on a second side of the memory array opposite the first side of the memory array, wherein each of the memory banks extends in a second direction different from the first direction and comprises a plurality of nonvolatile memory cells, each of the nonvolatile memory cells having a variable resistive element whose resistance value varies according to data stored therein.

摘要翻译： 非易失性存储器件包括：存储器阵列，包括沿第一方向布置的多个存储体; 写入全局位线和在第一方向上延伸以由存储体共享的读取全局位线; 写入电路，连接到写入全局位线并且设置在存储器阵列的第一侧上; 以及读取电路，连接到读取的全局位线并且设置在与存储器阵列的第一侧相对的存储器阵列的第二侧上，其中每个存储体沿与第一方向不同的第二方向延伸并且包括多个 的非易失性存储单元，每个非易失性存储单元具有可变电阻元件，其电阻值根据存储在其中的数据而变化。

公开(公告)号：US08120979B2

公开(公告)日：2012-02-21

申请号：US12591254

申请日：2009-11-13

申请人： Jin-Young Kim ,  Ki-Whan Song

发明人： Jin-Young Kim ,  Ki-Whan Song

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C11/4097 ,  G11C2207/002

摘要： The semiconductor memory device includes a memory cell array and a switching circuit. The memory cell array includes a plurality of first memory cells connected between word lines and first local bit lines, and a plurality of second memory cells connected between the word lines and second local bit lines. The switching circuit is configured to respectively connect the first local bit lines to first global bit lines during a first sensing period, and to respectively connect the second local bit lines to second global bit lines during a second sensing period of a reading operation. The semiconductor memory device further includes a sensing circuit configured to sense and amplify data from the first global bit lines during the first sensing period, and to sense and amplify data from the second global bit lines during the second sensing period of the reading operation.

摘要翻译： 半导体存储器件包括存储单元阵列和开关电路。 存储单元阵列包括连接在字线和第一局部位线之间的多个第一存储单元，以及连接在字线和第二局部位线之间的多个第二存储单元。 开关电路被配置为在第一感测周期期间将第一本地位线分别连接到第一全局位线，并且在读取操作的第二感测周期期间将第二局部位线分别连接到第二全局位线。 半导体存储器件还包括感测电路，其被配置为在第一感测周期期间感测和放大来自第一全局位线的数据，并且在读取操作的第二感测周期期间感测和放大来自第二全局位线的数据。