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公开(公告)号：US09608567B2
公开(公告)日：2017-03-28
申请号：US14123004
申请日：2011-05-30
申请人： Mikael Egard , Mats Ärlelid , Lars-Erik Wernersson
发明人： Mikael Egard , Mats Ärlelid , Lars-Erik Wernersson
IPC分类号： H04B1/38 , H03B7/08 , H04B1/7163
CPC分类号： H03B7/08 , H03B2200/0046 , H04B1/38 , H04B1/7163
摘要： A transceiver comprising a tank circuit, a variable differential conductance, VDC, coupled to the tank circuit, and a variable resistance coupled to the VDC is disclosed. The variable resistance is arranged to bias the VDC into a region of positive differential conductance during a first state of operation of the transceiver, and bias the VDC into a region of negative differential conductance during a second state of operation of the transceiver.
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公开(公告)号：US08344361B2
公开(公告)日：2013-01-01
申请号：US11922242
申请日：2006-06-16
IPC分类号： H01L51/00 , H01L29/94 , H01L29/76 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/165 , H01L29/205 , H01L29/775
摘要： The present invention relates to nanoscaled electronic devices with a vertical nanowire as a functional part. Contacts are arranged on the nanowire at different parts of the nanowire, for example drain and source contacts. In connection to the nanowire contacts are external electrodes, that connect at different levels, as seen from the substrate, of the device. The external electrodes are elongated, and typically and preferably stripe-like. According to the invention a first external electrode, or contacts, associated with contact(s) at a first part of the nanowire, and a second external electrode, associated with contact(s) at a second part of the nanowire are arranged in a cross-bar configuration. The cross-bar configuration minimizes the overlay of the external electrodes, hence, parasitic capacitances and current leakage can be reduced, and the performance of the device improved.
摘要翻译： 本发明涉及具有垂直纳米线作为功能部件的纳米级电子器件。 触点设置在纳米线的不同部分的纳米线上，例如漏极和源极触点。 与纳米线接触相关的是外部电极，其连接在不同的水平，如从衬底所看到的那样。 外部电极是细长的，并且通常且优选条纹状。 根据本发明，与纳米线的第一部分处的接触相关联的第一外部电极或触点和与纳米线的第二部分处的接触相关联的第二外部电极被布置成十字形 - 栏配置。 横杆配置使外部电极的覆盖最小化，因此可以减小寄生电容和电流泄漏，并且改善器件的性能。
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公开(公告)号：US08330143B2
公开(公告)日：2012-12-11
申请号：US11922243
申请日：2006-06-16
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/165 , H01L29/205 , H01L29/775
摘要： A nanowire wrap-gate transistor is realized in a semiconductor material with a band gap narrower than Si. The strain relaxation in the nanowires allows the transistor to be placed on a large variety of substrates and heterostructures to be incorporated in the device. Various types of heterostructures should be introduced in the transistor to reduce the output conductance via reduced impact ionization rate, increase the current on/off ratio, reduction of the sub-threshold slope, reduction of transistor contact resistance and improved thermal stability. The parasitic capacitances should be minimized by the use of semi-insulating substrates and the use of cross-bar geometry between the source and drain access regions. The transistor may find applications in digital high frequency and low power circuits as well as in analogue high frequency circuits.
摘要翻译： 在具有比Si窄的带隙的半导体材料中实现纳米线缠绕晶体管。 纳米线中的应变弛豫允许将晶体管放置在多种衬底和异质结构中以被并入器件中。 应在晶体管中引入各种类型的异质结，通过减小冲击电离速率，增加电流开/关比，降低子阈值斜率，降低晶体管接触电阻，提高热稳定性，从而降低输出电导。 应通过使用半绝缘基板和在源极和漏极访问区域之间使用横杆几何形状来最小化寄生电容。 晶体管可以在数字高频和低功率电路以及模拟高频电路中使用。
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4.发明授权Method of producing precision vertical and horizontal layers in a vertical semiconductor structure 有权在垂直半导体结构中制造精密垂直和水平层的方法公开(公告)号：US08178403B2
公开(公告)日：2012-05-15
申请号：US12441223
申请日：2007-09-18
IPC分类号： H01L21/76
CPC分类号： H01L29/7827 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/125 , H01L29/495 , H01L29/517 , H01L29/66439 , H01L29/66666 , H01L29/775 , H01L29/7828 , H01L29/78642 , H01L33/24 , Y10S977/888 , Y10S977/89
摘要： The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic deposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.
摘要翻译： 本发明涉及在垂直半导体器件（1）的垂直和水平表面（15,20）上提供不同厚度的层。 特别地，本发明涉及栅电极和在半导体结构中形成精密层（28），该半导体结构包括基底（10）和基本上从基底上竖立的细长结构（5）。 根据本发明的方法，将装置（1）的垂直几何结构与各向异性沉积或各向异性去除沉积材料结合使用以形成非常高精度的垂直或水平层。
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公开(公告)号：US20180219084A1
公开(公告)日：2018-08-02
申请号：US15738274
申请日：2016-06-21
IPC分类号： H01L29/66 , H01L29/423 , H01L29/40 , H01L29/06
CPC分类号： H01L29/66666 , B82Y10/00 , B82Y40/00 , H01L29/0676 , H01L29/068 , H01L29/401 , H01L29/42376 , H01L29/66469 , H01L29/66522 , H01L29/7391 , H01L29/775
摘要： A method for fabrication of vertical nanowire MOSFETs is considered using a gate-last process. The top ohmic electrode is first fabricated and may be used as a mask to form a gate recess using etching techniques. The gate is thereafter formed allowing a large degree in access resistance reduction.
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6.发明授权公开(公告)号：US09117753B2
公开(公告)日：2015-08-25
申请号：US14123479
申请日：2012-06-01
申请人： Mikael Egard , Erik Lind , Lars-Erik Wernersson
发明人： Mikael Egard , Erik Lind , Lars-Erik Wernersson
IPC分类号： H01L21/28 , H01L29/423 , H01L29/66 , H01L21/311 , H01L29/20 , H01L29/49 , H01L29/51 , H01L29/778 , H01L21/8234 , H01L21/84
CPC分类号： H01L21/28114 , H01L21/31144 , H01L21/823431 , H01L21/8252 , H01L21/845 , H01L27/0605 , H01L27/0629 , H01L29/20 , H01L29/42316 , H01L29/4236 , H01L29/42376 , H01L29/495 , H01L29/517 , H01L29/66462 , H01L29/66469 , H01L29/66522 , H01L29/6653 , H01L29/66545 , H01L29/66795 , H01L29/66871 , H01L29/7787
摘要： According to one aspect of the inventive concept there is provided a process for manufacturing a semiconductor device, comprising: providing a channel layer (104), providing a mask (106) on the channel layer, epitaxially growing a contact layer (108) in contact with the channel layer, epitaxially growing a support layer (110) on the contact layer, wherein the support layer is arranged to be etched at a higher rate than the contact layer, forming a trench extending through the support layer by removing the mask, and providing a conductor (118) in the trench. There is also provided an intermediate product for the manufacture of a semiconductor device.
摘要翻译： 根据本发明构思的一个方面，提供了一种用于制造半导体器件的方法，包括：提供沟道层（104），在沟道层上提供掩模（106），外延生长接触层（108） 与所述沟道层一起在所述接触层上外延生长支撑层（110），其中所述支撑层布置成以比所述接触层更高的速率进行蚀刻，通过移除所述掩模形成延伸穿过所述支撑层的沟槽，以及 在沟槽中提供导体（118）。 还提供了用于制造半导体器件的中间产品。
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7.发明申请METHOD OF PRODUCING PRECISION VERTICAL AND HORIZONTAL LAYERS IN A VERTICAL SEMICONDUCTOR STRUCTURE 审中-公开在垂直半导体结构中制造精密垂直层和水平层的方法公开(公告)号：US20140103423A1
公开(公告)日：2014-04-17
申请号：US14048502
申请日：2013-10-08
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/125 , H01L29/495 , H01L29/517 , H01L29/66439 , H01L29/66666 , H01L29/775 , H01L29/7828 , H01L29/78642 , H01L33/24 , Y10S977/888 , Y10S977/89
摘要： The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic deposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.
摘要翻译： 本发明涉及在垂直半导体器件（1）的垂直和水平表面（15,20）上提供不同厚度的层。 特别地，本发明涉及栅电极和在半导体结构中形成精密层（28），该半导体结构包括基底（10）和基本上从基底上竖立的细长结构（5）。 根据本发明的方法，将装置（1）的垂直几何结构与各向异性沉积或各向异性去除沉积材料结合使用以形成非常高精度的垂直或水平层。
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公开(公告)号：US20140098845A1
公开(公告)日：2014-04-10
申请号：US14123004
申请日：2011-05-30
申请人： Mikael Egard , Mats Ärlelid , Lars-Erik Wernersson
发明人： Mikael Egard , Mats Ärlelid , Lars-Erik Wernersson
CPC分类号： H03B7/08 , H03B2200/0046 , H04B1/38 , H04B1/7163
摘要： A transceiver comprising a tank circuit, a variable differential conductance, VDC, coupled to the tank circuit, and a variable resistance coupled to the VDC is disclosed. The variable resistance is arranged to bias the VDC into a region of positive differential conductance during a first state of operation of the transceiver, and bias the VDC into a region of negative differential conductance during a second state of operation of the transceiver.
摘要翻译： 公开了一种收发器，其包括耦合到储能电路的储能电路，可变差分电导率VDC和耦合到VDC的可变电阻。 可变电阻被布置成在收发器的第一操作状态期间将VDC偏置成正差分电导的区域，并且在收发器的第二操作状态期间将VDC偏置为负差分电导的区域。
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9.发明申请Method of Producing Precision Vertical and Horizontal Layers in a Vertical Semiconductor Structure 有权在垂直半导体结构中制造精密垂直和水平层的方法公开(公告)号：US20120211727A1
公开(公告)日：2012-08-23
申请号：US13458310
申请日：2012-04-27
IPC分类号： H01L29/775 , H01L21/283 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/7827 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/125 , H01L29/495 , H01L29/517 , H01L29/66439 , H01L29/66666 , H01L29/775 , H01L29/7828 , H01L29/78642 , H01L33/24 , Y10S977/888 , Y10S977/89
摘要： The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic desposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.
摘要翻译： 本发明涉及在垂直半导体器件（1）的垂直和水平表面（15,20）上提供不同厚度的层。 特别地，本发明涉及栅电极和在半导体结构中形成精密层（28），该半导体结构包括基底（10）和基本上从基底上竖立的细长结构（5）。 根据本发明的方法，将装置（1）的垂直几何结构与各向异性沉积或各向异性去除沉积材料结合使用以形成非常高精度的垂直或水平层。
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公开(公告)号：US08063450B2
公开(公告)日：2011-11-22
申请号：US12441220
申请日：2007-09-19
申请人： Lars-Erik Wernersson , Erik Lind , Tomas Bryllert , Jonas Ohlsson , Truls Löwgren , Lars Samuelson , Claes Thelander
发明人： Lars-Erik Wernersson , Erik Lind , Tomas Bryllert , Jonas Ohlsson , Truls Löwgren , Lars Samuelson , Claes Thelander
IPC分类号： H01L27/088
CPC分类号： H01L27/0883 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/20 , H01L29/775 , H01L29/7828
摘要： The present invention relates to vertical nanowire transistors with a wrap-gated geometry. The threshold voltage of the vertical nanowire transistors is controlled by the diameter of the nanowire, the doping of the nanowire, the introduction of segments of heterostructures in the nanowire, the doping in shell-structures surrounding the nanowire, tailoring the work function of the gate stack, by strain engineering, by control of the dielectrica or the choice of nanowire material. Transistors with varying threshold voltages are provided on the same substrate, which enables the design of advanced circuits utilizing the shifts in the threshold voltages, similar to the directly coupled field logic.
摘要翻译： 本发明涉及具有封盖几何形状的垂直纳米线晶体管。 垂直纳米线晶体管的阈值电压由纳米线的直径，纳米线的掺杂，纳米线中的异质结构段的引入，纳米线周围的壳结构中的掺杂来调节，栅极的功函数 堆叠，通过应变工程，通过控制电介质或纳米线材料的选择。 具有不同阈值电压的晶体管设置在相同的基板上，这使得能够利用阈值电压的偏移设计高级电路，类似于直接耦合的场逻辑。
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