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    Technique for improving negative potential immunity of an integrated circuit
    3.
    发明申请
    Technique for improving negative potential immunity of an integrated circuit 有权
    提高集成电路的负电位抗扰度的技术

    公开(公告)号：US20070096776A1

    公开(公告)日：2007-05-03

    申请号：US11261310

    申请日：2005-10-28

    申请人： Mark Gose ,  John Grawcock

    发明人： Mark Gose ,  John Grawcock

    IPC分类号： H03B1/00

    CPC分类号： H03K17/0822 ,  H01L29/7816

    摘要： An integrated circuit (IC) with negative potential protection includes a switch, a gate drive circuit and a comparator. The switch includes a double-diffused metal-oxide semiconductor (DMOS) cell formed in a first-type epitaxial pocket, which is formed in a second-type substrate. The switch also includes a second-type+ isolation ring formed in the substrate to isolate the first-type epitaxial pocket. An output of the gate drive circuit is coupled across a gate and a source of the switch. An output of the comparator is coupled to a second input of the gate drive circuit and a first input of the comparator receives a reference signal. A second input of the comparator is coupled to the epitaxial pocket. The comparator provides a turn-on signal that causes the switch to conduct current, when a signal at the second input of the comparator is below the reference signal.

    摘要翻译： 具有负电位保护的集成电路（IC）包括开关，栅极驱动电路和比较器。 该开关包括形成在第二型衬底中的第一型外延袋中形成的双扩散金属氧化物半导体（DMOS）单元。 开关还包括形成在衬底中以隔离第一类型外延袋的第二类型+隔离环。 栅极驱动电路的输出端跨越开关的栅极和源极耦合。 比较器的输出耦合到栅极驱动电路的第二输入，比较器的第一输入接收参考信号。 比较器的第二输入耦合到外延袋。 当比较器的第二输入端的信号低于参考信号时，比较器提供导通开关导通电流的导通信号。

    TECHNIQUE FOR DETERMINING A LOAD CURRENT
    4.
    发明申请
    TECHNIQUE FOR DETERMINING A LOAD CURRENT 有权
    确定负载电流的技术

    公开(公告)号：US20070052454A1

    公开(公告)日：2007-03-08

    申请号：US11220767

    申请日：2005-09-07

    申请人： Mark Gose ,  Douglas Osborn

    发明人： Mark Gose ,  Douglas Osborn

    IPC分类号： H03B1/00

    CPC分类号： H03F3/347 ,  G01R19/0092 ,  H03F2200/321 ,  H03F2200/462

    摘要： An integrated driver with improved load current sense capability includes a first transistor, a first amplifier, a second transistor, a third transistor, a second amplifier and a fourth transistor. The integrated driver allows for significantly better fault handling capability, provides accurate thermal and current sensing capability and reduces I/O pin count over prior designs.

    摘要翻译： 具有改进的负载电流检测能力的集成驱动器包括第一晶体管，第一放大器，第二晶体管，第三晶体管，第二放大器和第四晶体管。 集成驱动器可显着提高故障处理能力，提供精确的热和电流检测功能，并减少I / O引脚数量超过以前的设计。

    Flip-chip interconnect with increased current-carrying capability
    5.
    发明申请
    Flip-chip interconnect with increased current-carrying capability 审中-公开
    倒装芯片互连具有增加的载流能力

    公开(公告)号：US20050046024A1

    公开(公告)日：2005-03-03

    申请号：US10961446

    申请日：2004-10-08

    申请人： Pankaj Mithal ,  William Higdon ,  Mark Gose ,  John Dikeman ,  Frank Stepniak

    发明人： Pankaj Mithal ,  William Higdon ,  Mark Gose ,  John Dikeman ,  Frank Stepniak

    IPC分类号： H01L23/485 ,  H01L23/528 ,  H01L21/44

    CPC分类号： H01L24/02 ,  H01L23/528 ,  H01L24/10 ,  H01L2224/0401 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14

    摘要： A metal runner that improves the current-carrying capability of solder bumps used to electrically connect a surface-mount circuit device to a substrate. The runner comprises at least one leg portion and a pad portion, with the pad portion having a continuous region and a plurality of separate electrical paths leading to and from the continuous region. The electrical paths are delineated in the pad portion by nonconductive regions defined in the pad portion, with at least some of the nonconductive regions extending into the leg portion. The multiple electrical paths split the current flow to and from the solder bump, distributing the current around the perimeter of the solder bump in a manner that reduces current density in regions of the solder bump where electromigration is most likely.

    摘要翻译： 金属流道，其提高用于将表面贴装电路器件电连接到衬底的焊料凸块的载流能力。 流道包括至少一个支腿部分和垫部分，其中该焊盘部分具有连续区域和连续区域的多个分开的电路径。 在焊盘部分中通过限定在焊盘部分中的非导电区域描绘电路径，其中至少一些非导电区域延伸到腿部。 多个电路径将电流流向和从焊料凸块分开，以在减少电子迁移最有可能的焊料凸块区域中的电流密度的方式将电流分布在焊料凸块的周边周围。