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公开(公告)号：US07566866B2
公开(公告)日：2009-07-28
申请号：US11852506
申请日：2007-09-10
Applicant: Mark Vandermeulen , Robert E. Hawke , David Roy , William F. Hill
Inventor： Mark Vandermeulen , Robert E. Hawke , David Roy , William F. Hill
IPC: H01J40/14
CPC classification number: G01J1/02 , G01J1/0271 , G01J1/04 , G01J1/0403 , H05K3/3436 , H05K2201/094 , H05K2201/10121 , H05K2201/10484 , Y02P70/613
Abstract: Systems and methods are provided for depositing solder in a first pattern over a first bonding pad on the substrate; depositing solder in a second pattern over a second bonding pad on the substrate, wherein the second pattern defines a larger area than the first pattern; placing the electronic device on the substrate such that pads on the electronic device are aligned with the first and second bonding pads; and reflowing the solder between the pads on the electronic device and the first and second bonding pads, causing the solder deposited on the first bonding pad to form a first solder joint and the solder deposited on the second bonding pad to form a second solder joint. The second solder joint is larger than the first solder joint causing the electronic device to be attached at an angle relative to the substrate.
Abstract translation: 提供了用于在衬底上的第一焊盘上以第一图案沉积焊料的系统和方法; 在衬底上的第二接合焊盘上以第二图案沉积焊料，其中所述第二图案限定比所述第一图案更大的面积; 将所述电子设备放置在所述基板上，使得所述电子设备上的焊盘与所述第一和第二焊盘对准; 以及在所述电子设备上的所述焊盘与所述第一和第二接合焊盘之间回流焊料，使得沉积在所述第一接合焊盘上的所述焊料形成第一焊接接头，并且所述焊料沉积在所述第二接合焊盘上以形成第二焊接接头。 第二焊点比第一焊点大，导致电子器件相对于衬底以一定角度附着。
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公开(公告)号：US07224040B2
公开(公告)日：2007-05-29
申请号：US10997344
申请日：2004-11-24
Applicant: Ivoyl P. Koutsaroff , Mark Vandermeulen , Andrew Cervin-Lawry , Atin J. Patel
Inventor： Ivoyl P. Koutsaroff , Mark Vandermeulen , Andrew Cervin-Lawry , Atin J. Patel
IPC: H01L29/00
CPC classification number: H01L27/016 , H01G4/1227 , H01G4/33 , H01L23/49822 , H01L28/40 , H01L2924/09701 , H01L2924/15787 , H05K1/0306 , H05K1/16
Abstract: In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).
Abstract translation: 根据本文所述的教导，提供了陶瓷基板上的多层薄膜电容器及其制造方法。 多层薄膜电容器（MLC）可以在至少两个电极层之间包括至少一个高介电常数介电层，电极层由导电薄膜材料形成。 陶瓷基板和薄膜MLC之间可以包括缓冲层。 缓冲层可以具有小于或等于0.08微米（μm）的表面粗糙度（Ra）的光滑表面。
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3.发明申请Multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same 有权陶瓷基板上的多层薄膜电容器及其制造方法公开(公告)号：US20050117272A1
公开(公告)日：2005-06-02
申请号：US10997344
申请日：2004-11-24
Applicant: Ivoyl Koutsaroff , Mark Vandermeulen , Andrew Cervin-Lawry , Atin Patel
Inventor： Ivoyl Koutsaroff , Mark Vandermeulen , Andrew Cervin-Lawry , Atin Patel
CPC classification number: H01L27/016 , H01G4/1227 , H01G4/33 , H01L23/49822 , H01L28/40 , H01L2924/09701 , H01L2924/15787 , H05K1/0306 , H05K1/16
Abstract: In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).
Abstract translation: 根据本文所述的教导，提供了陶瓷基板上的多层薄膜电容器及其制造方法。 多层薄膜电容器（MLC）可以在至少两个电极层之间包括至少一个高介电常数介电层，电极层由导电薄膜材料形成。 陶瓷基板和薄膜MLC之间可以包括缓冲层。 缓冲层可以具有小于或等于0.08微米（μm）的表面粗糙度（Ra）的光滑表面。
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公开(公告)号：US06583019B2
公开(公告)日：2003-06-24
申请号：US09992678
申请日：2001-11-19
Applicant: Mark Vandermeulen , David Roy
Inventor： Mark Vandermeulen , David Roy
IPC: H01L2120
CPC classification number: H05K3/3452 , H01L23/49816 , H01L23/49838 , H01L2924/0002 , H01L2924/09701 , H05K1/092 , H05K2201/09481 , H05K2201/099 , H01L2924/00
Abstract: A thick film circuit with a perimeter anchored thick film pad is provided. The thick film circuit includes a base substrate, a thick film bonding pad, and a solder mask layer. The thick film bonding pad is formed on the surface of the base substrate. The solder mask layer is also formed on the surface of the base substrate, and overlaps a portion of the thick film bonding pad in order to improve adhesion between the thick film bonding pad and the base substrate.
Abstract translation: 提供了具有周边锚定厚膜垫的厚膜电路。 厚膜电路包括基底基板，厚膜接合焊盘和焊接掩模层。 在基板的表面上形成厚膜接合焊盘。 焊接掩模层也形成在基底基板的表面上，并且与厚膜接合焊盘的一部分重叠，以便改善厚膜焊盘和基底基板之间的粘合。
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5.发明申请Multi-Level Thin Film Capacitor on a Ceramic Substrate and Method of Manufacturing the Same 有权陶瓷基板上的多层薄膜电容器及其制造方法公开(公告)号：US20080037200A1
公开(公告)日：2008-02-14
申请号：US11734798
申请日：2007-04-13
Applicant: Ivoyl Koutsaroff , Mark Vandermeulen , Andrew Cervin-Lawry , Atin Patel
Inventor： Ivoyl Koutsaroff , Mark Vandermeulen , Andrew Cervin-Lawry , Atin Patel
IPC: H01G4/06
CPC classification number: H01L27/016 , H01G4/1227 , H01G4/33 , H01L23/49822 , H01L28/40 , H01L2924/09701 , H01L2924/15787 , H05K1/0306 , H05K1/16
Abstract: In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).
Abstract translation: 根据本文所述的教导，提供了陶瓷基板上的多层薄膜电容器及其制造方法。 多层薄膜电容器（MLC）可以在至少两个电极层之间包括至少一个高介电常数介电层，电极层由导电薄膜材料形成。 陶瓷基板和薄膜MLC之间可以包括缓冲层。 缓冲层可以具有小于或等于0.08微米（μm）的表面粗糙度（Ra）的光滑表面。
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Patent Agency Ranking
6.发明申请MULTI-LEVEL THIN FILM CAPACITOR ON A CERAMIC SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权陶瓷基板上的多层薄膜电容器及其制造方法公开(公告)号：US20070209201A1
公开(公告)日：2007-09-13
申请号：US11736408
申请日：2007-04-17
Applicant: Ivoyl Koutsaroff , Mark Vandermeulen , Andrew Cervin-Lawry , Atin Patel
Inventor： Ivoyl Koutsaroff , Mark Vandermeulen , Andrew Cervin-Lawry , Atin Patel
CPC classification number: H01G4/38 , H01G4/33 , H01G13/04 , H01L27/016 , H05K1/0306 , H05K1/162 , H05K3/38 , H05K3/388 , H05K2201/0175 , H05K2201/0179 , Y10T29/49126 , Y10T29/49155
Abstract: In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).
Abstract translation: 根据本文所述的教导，提供了陶瓷基板上的多层薄膜电容器及其制造方法。 多层薄膜电容器（MLC）可以在至少两个电极层之间包括至少一个高介电常数介电层，电极层由导电薄膜材料形成。 陶瓷基板和薄膜MLC之间可以包括缓冲层。 缓冲层可以具有小于或等于0.08微米（μm）的表面粗糙度（Ra）的光滑表面。
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7.发明授权Multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same 有权陶瓷基板上的多层薄膜电容器及其制造方法公开(公告)号：US08569142B2
公开(公告)日：2013-10-29
申请号：US11736408
申请日：2007-04-17
Applicant: Ivoyl P. Koutsaroff , Mark Vandermeulen , Andrew Cervin-Lawry , Atin J. Patel
Inventor： Ivoyl P. Koutsaroff , Mark Vandermeulen , Andrew Cervin-Lawry , Atin J. Patel
IPC: H01L21/20
CPC classification number: H01G4/38 , H01G4/33 , H01G13/04 , H01L27/016 , H05K1/0306 , H05K1/162 , H05K3/38 , H05K3/388 , H05K2201/0175 , H05K2201/0179 , Y10T29/49126 , Y10T29/49155
Abstract: In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).
Abstract translation: 根据本文所述的教导，提供了陶瓷基板上的多层薄膜电容器及其制造方法。 多层薄膜电容器（MLC）可以在至少两个电极层之间包括至少一个高介电常数介电层，电极层由导电薄膜材料形成。 陶瓷基板和薄膜MLC之间可以包括缓冲层。 缓冲层可以具有小于或等于0.08微米（μm）的表面粗糙度（Ra）的光滑表面。
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8.发明授权Multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same 有权陶瓷基板上的多层薄膜电容器及其制造方法公开(公告)号：US07875956B2
公开(公告)日：2011-01-25
申请号：US11734798
申请日：2007-04-17
Applicant: Ivoyl P. Koutsaroff , Mark Vandermeulen , Andrew Cervin-Lawry , Atin J. Patel
Inventor： Ivoyl P. Koutsaroff , Mark Vandermeulen , Andrew Cervin-Lawry , Atin J. Patel
IPC: H01L51/05
CPC classification number: H01L27/016 , H01G4/1227 , H01G4/33 , H01L23/49822 , H01L28/40 , H01L2924/09701 , H01L2924/15787 , H05K1/0306 , H05K1/16
Abstract: In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).
Abstract translation: 根据本文所述的教导，提供了陶瓷基板上的多层薄膜电容器及其制造方法。 多层薄膜电容器（MLC）可以在至少两个电极层之间包括至少一个高介电常数介电层，电极层由导电薄膜材料形成。 陶瓷基板和薄膜MLC之间可以包括缓冲层。 缓冲层可以具有小于或等于0.08微米（μm）的表面粗糙度（Ra）的光滑表面。
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公开(公告)号：US20090087010A1
公开(公告)日：2009-04-02
申请号：US11862471
申请日：2007-09-27
Applicant: Mark Vandermeulen , David Roy , Charles Divita
Inventor： Mark Vandermeulen , David Roy , Charles Divita
IPC: H04R1/02
CPC classification number: H04R31/00
Abstract: A microphone apparatus includes a carrier chip and a microphone chip. The carrier chip includes a substrate with parallel top and bottom surfaces, a metallization layer overlying the top surface, and a cylindrical cavity that is bored through the top surface and the metallization layer and partially through the carrier substrate. The microphone chip includes a substrate with parallel top and bottom surfaces, a cylindrical cavity extending from the microphone substrate top surface to the microphone substrate bottom surface, and a diaphragm attached to the microphone substrate bottom surface and extending across the microphone cavity. The microphone chip is fixed to the carrier chip, with the microphone cavity overlying the carrier cavity, and the diaphragm covering the carrier cavity and electrically connected to the metallization layer.
Abstract translation: 麦克风装置包括载体芯片和麦克风芯片。 载体芯片包括具有平行的顶表面和底表面的基底，覆盖顶表面的金属化层，以及穿过顶表面和金属化层并部分穿过载体基底的圆柱形腔。 麦克风芯片包括具有平行的顶部和底部表面的基板，从麦克风基板顶表面延伸到麦克风基板底部表面的圆柱形腔体，以及附接到麦克风基板底部表面并延伸穿过麦克风腔体的隔膜。 麦克风芯片固定在载体芯片上，麦克风腔覆盖载体腔，隔膜覆盖载体腔并与金属化层电连接。
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公开(公告)号：US20090065678A1
公开(公告)日：2009-03-12
申请号：US11852506
申请日：2007-09-10
Applicant: Mark Vandermeulen , Robert E. Hawke , David Roy , William F. Hill
Inventor： Mark Vandermeulen , Robert E. Hawke , David Roy , William F. Hill
CPC classification number: G01J1/02 , G01J1/0271 , G01J1/04 , G01J1/0403 , H05K3/3436 , H05K2201/094 , H05K2201/10121 , H05K2201/10484 , Y02P70/613
Abstract: Systems and methods are provided for depositing solder in a first pattern over a first bonding pad on the substrate; depositing solder in a second pattern over a second bonding pad on the substrate, wherein the second pattern defines a larger area than the first pattern; placing the electronic device on the substrate such that pads on the electronic device are aligned with the first and second bonding pads; and reflowing the solder between the pads on the electronic device and the first and second bonding pads, causing the solder deposited on the first bonding pad to form a first solder joint and the solder deposited on the second bonding pad to form a second solder joint. The second solder joint is larger than the first solder joint causing the electronic device to be attached at an angle relative to the substrate.
Abstract translation: 提供了用于在衬底上的第一焊盘上以第一图案沉积焊料的系统和方法; 在衬底上的第二接合焊盘上以第二图案沉积焊料，其中所述第二图案限定比所述第一图案更大的面积; 将所述电子设备放置在所述基板上，使得所述电子设备上的焊盘与所述第一和第二焊盘对准; 以及在所述电子设备上的所述焊盘与所述第一和第二接合焊盘之间回流焊料，使得沉积在所述第一接合焊盘上的所述焊料形成第一焊接接头，并且所述焊料沉积在所述第二接合焊盘上以形成第二焊接接头。 第二焊点比第一焊点大，导致电子器件相对于衬底以一定角度附着。
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