Method and system for intra-pulse frequency estimation against agile emitters

    公开(公告)号:US11054502B2

    公开(公告)日:2021-07-06

    申请号:US16046508

    申请日:2018-07-26

    发明人: Robert Liechty

    IPC分类号: G01S7/41 G01S7/292

    摘要: A radar detection system that estimates the received pulse frequency of a pulse in a received radar signal using a signal transmit frequency or one that uses frequency agility during a pulse duration. The radar detector system may include a radar detector that receives the radar signal from an antenna or antenna array. The receiver may be channelized, and each channel path may include Gaussian bandpass filter(s) centered at a different frequencies. The system includes an extended range radar detector that receives the signal in the channels and processing logic that processes the detected channel signals to identify the pulse frequency of emitters with or without frequency agility during a pulse duration. The frequency estimates of the pulse are based on calibrated amplitude differences in adjacent channels.

    Radial power combiner/divider using dielectrically loaded waveguides

    公开(公告)号:US10381705B2

    公开(公告)日:2019-08-13

    申请号:US15625368

    申请日:2017-06-16

    IPC分类号: H01P5/12

    摘要: A power combiner/power divider has a disk shaped housing cavity and a housing of electrically conductive material, such as metal. A junction pin is positioned centrally in the power combiner/divider. Additional ports are positioned radially along the periphery of the disk shaped portion. Tapered waveguides may extend from the radially positioned ports to the centrally positioned junction pin. A hollow radial cavity provided in the cavity holds a dielectric insert that may have tapering extensions radiating from a central ring. The ring surrounds the centrally positioned port.

    Multi-voltage to isolated logic level trigger

    公开(公告)号:US09722608B2

    公开(公告)日:2017-08-01

    申请号:US15217294

    申请日:2016-07-22

    摘要: Various systems may benefit from interfaces for handling multiple types of inputs. For example, a device with a trigger input from an external device may benefit from an isolated logic level trigger that is capable of addressing multiple types and values of voltage. An apparatus can include an input configured to receive an external trigger input signal having a trigger input voltage. The apparatus can also include circuitry configured to automatically adjust the trigger input voltage to a value configured to be compatible with a provided attached system. A working range of the trigger input voltage can exceed a compatible working range of the provided attached system.

    METHOD AND SYSTEM FOR INTRA-PULSE FREQUENCY ESTIMATION AGAINST AGILE EMITTERS

    公开(公告)号:US20210165087A1

    公开(公告)日:2021-06-03

    申请号:US16046508

    申请日:2018-07-26

    发明人: Robert Liechty

    IPC分类号: G01S13/24 G01S7/34 G01S13/20

    摘要: A radar detection system that estimates the received pulse frequency of a pulse in a received radar signal using a signal transmit frequency or one that uses frequency agility during a pulse duration. The radar detector system may include a radar detector that receives the radar signal from an antenna or antenna array. The receiver may be channelized, and each channel path may include Gaussian bandpass filter(s) centered at a different frequencies. The system includes an extended range radar detector that receives the signal in the channels and processing logic that processes the detected channel signals to identify the pulse frequency of emitters with or without frequency agility during a pulse duration. The frequency estimates of the pulse are based on calibrated amplitude differences in adjacent channels.

    Multi-Voltage to Isolated Logic Level Trigger
    7.
    发明申请
    Multi-Voltage to Isolated Logic Level Trigger 有权
    多电压到隔离逻辑电平触发

    公开(公告)号:US20170026043A1

    公开(公告)日:2017-01-26

    申请号:US15217294

    申请日:2016-07-22

    IPC分类号: H03K19/0185 H03K5/08

    摘要: Various systems may benefit from interfaces for handling multiple types of inputs. For example, a device with a trigger input from an external device may benefit from an isolated logic level trigger that is capable of addressing multiple types and values of voltage. An apparatus can include an input configured to receive an external trigger input signal having a trigger input voltage. The apparatus can also include circuitry configured to automatically adjust the trigger input voltage to a value configured to be compatible with a provided attached system. A working range of the trigger input voltage can exceed a compatible working range of the provided attached system.

    摘要翻译: 各种系统可能受益于用于处理多种类型的输入的接口。 例如,具有来自外部设备的触发输入的设备可以受益于能够寻址多种类型和电压值的隔离逻辑电平触发。 装置可以包括被配置为接收具有触发输入电压的外部触发输入信号的输入。 该装置还可以包括被配置为将触发输入电压自动调整为被配置为与所提供的附接系统兼容的值的电路。 触发输入电压的工作范围可能超过所提供的连接系统的兼容工作范围。

    Challenge/response system
    8.
    发明授权

    公开(公告)号:US10917250B2

    公开(公告)日:2021-02-09

    申请号:US15596494

    申请日:2017-05-16

    发明人: James M. Lewis

    摘要: A challenge/response system separates a physically unclonable function from the challenge/response. Bits in a challenge are used to qualify random data values. The random data values are permuted to generate a result. The result is used to encrypt a response that is sent in reply to the challenge. Additional permuting mechanisms may be used to further obfuscate the response.

    CHALLENGE/RESPONSE SYSTEM
    9.
    发明申请

    公开(公告)号:US20180337789A1

    公开(公告)日:2018-11-22

    申请号:US15596494

    申请日:2017-05-16

    发明人: James M. LEWIS

    IPC分类号: H04L9/32 H04L29/06

    摘要: A challenge/response system separates a physically unclonable function from the challenge/response. Bits in a challenge are used to qualify random data values. The random data values are permuted to generate a result. The result is used to encrypt a response that is sent in reply to the challenge. Additional permuting mechanisms may be used to further obfuscate the response.