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    METHOD OF FABRICATING A GATE STRUCTURE
    2.
    发明申请
    METHOD OF FABRICATING A GATE STRUCTURE 审中-公开
    制作门结构的方法

    公开(公告)号：US20090311855A1

    公开(公告)日：2009-12-17

    申请号：US12544425

    申请日：2009-08-20

    申请人： Richard A. Bruff ,  Richard A. Conti ,  Denise Pendleton-Lipinski ,  Amanda L. Tessier ,  Brian L. Tessier ,  Yun-Yu Wang ,  Daewon Yang ,  Chienfan Yu

    发明人： Richard A. Bruff ,  Richard A. Conti ,  Denise Pendleton-Lipinski ,  Amanda L. Tessier ,  Brian L. Tessier ,  Yun-Yu Wang ,  Daewon Yang ,  Chienfan Yu

    IPC分类号： H01L21/28

    CPC分类号： H01L21/823807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/823864 ,  H01L29/7843

    摘要： A method of fabricating a gate structure in a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof is provided. The MOSFET may be n-doped or p-doped. The gate structure, disposed on a substrate, includes a plurality of gates. Each of the plurality of gates is separated by a vertical space from an adjacent gate. The method deposits at least one dual-layer liner over the gate structure filling each vertical space. The dual-layer liner includes at least two thin high density plasma (HDP) films. The deposition of both HDP films occurs in a single HDP chemical vapor deposition (CVD) process. The dual-layer liner has properties conducive for coupling with plasma enhanced chemical vapor deposition (PECVD) films to form tri-layer or quadric-layer film stacks in the gate structure.

    摘要翻译： 提供了在金属氧化物半导体场效应晶体管（MOSFET）中制造栅极结构的方法及其结构。 MOSFET可以是n掺杂或p掺杂的。 设置在基板上的栅极结构包括多个栅极。 多个栅极中的每一个与相邻栅极分开一垂直空间。 该方法将填充每个垂直空间的至少一个双层衬垫沉积在栅极结构上。 双层衬垫包括至少两个薄的高密度等离子体（HDP）膜。 两种HDP膜的沉积在单个HDP化学气相沉积（CVD）工艺中发生。 双层衬垫具有有利于与等离子体增强化学气相沉积（PECVD）膜耦合以在栅极结构中形成三层或二次层膜堆叠的性质。

    METHOD OF FABRICATING A GATE STRUCTURE AND THE STRUCTURE THEREOF
    3.
    发明申请
    METHOD OF FABRICATING A GATE STRUCTURE AND THE STRUCTURE THEREOF 审中-公开
    制造门式结构的方法及其结构

    公开(公告)号：US20090101980A1

    公开(公告)日：2009-04-23

    申请号：US11875222

    申请日：2007-10-19

    申请人： Richard A. Bruff ,  Richard A. Conti ,  Denise Pendleton-Lipinski ,  Amanda L. Tessier ,  Brian L. Tessier ,  Yun-Yu Wang ,  Daewon Yang ,  Chienfan Yu

    发明人： Richard A. Bruff ,  Richard A. Conti ,  Denise Pendleton-Lipinski ,  Amanda L. Tessier ,  Brian L. Tessier ,  Yun-Yu Wang ,  Daewon Yang ,  Chienfan Yu

    IPC分类号： H01L27/088 ,  H01L21/3205

    CPC分类号： H01L21/823807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/823864 ,  H01L29/7843

    摘要： A method of fabricating a gate structure in a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof is provided. The MOSFET may be n-doped or p-doped. The gate structure, disposed on a substrate, includes a plurality of gates. Each of the plurality of gates is separated by a vertical space from an adjacent gate. The method deposits at least one dual-layer liner over the gate structure filling each vertical space. The dual-layer liner includes at least two thin high density plasma (HDP) films. The deposition of both HDP films occurs in a single HDP chemical vapor deposition (CVD) process. The dual-layer liner has properties conducive for coupling with plasma enhanced chemical vapor deposition (PECVD) films to form tri-layer or quadric-layer film stacks in the gate structure.

    摘要翻译： 提供了在金属氧化物半导体场效应晶体管（MOSFET）中制造栅极结构的方法及其结构。 MOSFET可以是n掺杂或p掺杂的。 设置在基板上的栅极结构包括多个栅极。 多个栅极中的每一个与相邻栅极分开一垂直空间。 该方法将填充每个垂直空间的至少一个双层衬垫沉积在栅极结构上。 双层衬垫包括至少两个薄的高密度等离子体（HDP）膜。 两种HDP膜的沉积在单个HDP化学气相沉积（CVD）工艺中发生。 双层衬垫具有有利于与等离子体增强化学气相沉积（PECVD）膜耦合以在栅极结构中形成三层或二次层膜堆叠的性质。

    Method of forming nitride films with high compressive stress for improved PFET device performance
    5.
    发明授权
    Method of forming nitride films with high compressive stress for improved PFET device performance 失效
    形成具有高压缩应力的氮化物薄膜以提高PFET器件性能的方法

    公开(公告)号：US07462527B2

    公开(公告)日：2008-12-09

    申请号：US11160705

    申请日：2005-07-06

    申请人： Richard A. Conti ,  Ronald P. Bourque ,  Nancy R. Klymko ,  Anita Madan ,  Michael C. Smits ,  Roy H. Tilghman ,  Kwong Hon Wong ,  Daewon Yang

    发明人： Richard A. Conti ,  Ronald P. Bourque ,  Nancy R. Klymko ,  Anita Madan ,  Michael C. Smits ,  Roy H. Tilghman ,  Kwong Hon Wong ,  Daewon Yang

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823828 ,  H01L29/7843

    摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

    摘要翻译： 提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。 这种压应力允许改进PFET中的器件性能。 使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。 偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。 在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。 氮化物层的厚度在约300-2000埃的范围内。

    MASK HAVING IMPLANT STOPPING LAYER
    6.
    发明申请
    MASK HAVING IMPLANT STOPPING LAYER 审中-公开
    掩蔽具有植入物停留层

    公开(公告)号：US20080286545A1

    公开(公告)日：2008-11-20

    申请号：US12145922

    申请日：2008-06-25

    申请人： Katherina Babich ,  Todd C. Bailey ,  Richard A. Conti ,  Ryan P. Deschner

    发明人： Katherina Babich ,  Todd C. Bailey ,  Richard A. Conti ,  Ryan P. Deschner

    IPC分类号： B32B7/02

    CPC分类号： H01L21/26513 ,  H01L21/266 ,  Y10T428/24992

    摘要： Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing an implant stopping layer over the substrate; depositing a photoresist over the implant stopping layer, the implant stopping layer having a density greater than the photoresist; forming a pattern in the photoresist by removing a portion of the photoresist to expose the implant stopping layer; and transferring the pattern into the implant stopping layer by etching to form the mask. The implant stopping layer may include: hydrogenated germanium carbide, nitrogenated germanium carbide, fluorinated germanium carbide, and/or amorphous germanium carbon hydride (GeHX), where X includes carbon. The methods/mask reduce scattering during implanting because the mask has higher density than conventional masks.

    摘要翻译： 形成用于植入衬底的掩模和使用具有光刻胶的注入阻挡层进行植入的方法提供了较低的纵横比掩模，其在去除掩模期间对衬底中的沟槽隔离造成最小的损害。 在一个实施例中，形成掩模的方法包括：在衬底上沉积注入阻挡层; 在所述注入阻挡层上沉积光致抗蚀剂，所述注入阻挡层的密度大于所述光致抗蚀剂; 通过去除光致抗蚀剂的一部分以暴露植入物停止层，在光致抗蚀剂中形成图案; 并通过蚀刻将图案转移到植入物停止层中以形成掩模。 注入停止层可以包括：氢化碳化锗，氮化碳化锗，氟化锗碳化物和/或无定形锗碳氢化物（GeHX），其中X包括碳。 方法/掩模减少了植入过程中的散射，因为掩模具有比常规掩模更高的密度。

    Self-aligned buried strap process using doped HDP oxide
    8.
    发明授权
    Self-aligned buried strap process using doped HDP oxide 失效
    使用掺杂HDP氧化物的自对准掩埋工艺

    公开(公告)号：US06667504B1

    公开(公告)日：2003-12-23

    申请号：US10249228

    申请日：2003-03-24

    申请人： Jochen Beintner ,  Wolfgang Bergner ,  Richard A. Conti ,  Andreas Knorr ,  Rolf Weis

    发明人： Jochen Beintner ,  Wolfgang Bergner ,  Richard A. Conti ,  Andreas Knorr ,  Rolf Weis

    IPC分类号： H01L27108

    CPC分类号： H01L27/10867 ,  H01L27/10864 ,  H01L29/945

    摘要： The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an undoped trench top oxide layer above the doped trench top oxide layer.

    摘要翻译： 本发明提供了一种沟槽存储结构，其包括具有沟槽的衬底，沟槽下部的电容器导体，与电容器导体相邻的沟槽中的导电节点带，电容器导体上方的沟槽顶部氧化物，以及导电 埋在衬底中的邻近沟槽顶部氧化物的衬底。 沟槽顶部氧化物包括导电带上方的掺杂沟槽顶部氧化物层和掺杂沟槽顶部氧化物层上方的未掺杂沟槽顶部氧化物层。

    High throughput chemical vapor deposition process capable of filling high aspect ratio structures
    9.
    发明授权
    High throughput chemical vapor deposition process capable of filling high aspect ratio structures 失效
    能够填充高纵横比结构的高通量化学气相沉积工艺

    公开(公告)号：US6030881A

    公开(公告)日：2000-02-29

    申请号：US72759

    申请日：1998-05-05

    申请人： George D. Papasouliotis ,  Ashima B. Chakravarti ,  Richard A. Conti ,  Laertis Economikos ,  Patrick A. Van Cleemput

    发明人： George D. Papasouliotis ,  Ashima B. Chakravarti ,  Richard A. Conti ,  Laertis Economikos ,  Patrick A. Van Cleemput

    IPC分类号： C23C16/04 ,  C23C16/40 ,  C23C16/56 ,  H01L21/762

    CPC分类号： H01L21/76224 ,  C23C16/045 ,  C23C16/401 ,  C23C16/56

    摘要： A method is provided for filling high aspect ratio gaps without void formation by using a high density plasma (HDP) deposition process with a sequence of deposition and etch steps having varying etch rate-to-deposition rate (etch/dep) ratios. The first step uses an etch/dep ratio less than one to quickly fill the gap. The first step is interrupted before the opening to the gap is closed. The second step uses an etch/dep ratio greater than one to widen the gap. The second step is stopped before corners of the elements forming the gaps are exposed. These steps can be repeated until the aspect ratio of the gap is reduced so that void-free gap-fill is possible. The etch/dep ratio and duration of each step can be optimized for high throughput and high aspect ratio gap-fill capacity.

    摘要翻译： 提供了一种通过使用具有不同蚀刻速率 - 沉积速率（蚀刻/去除）比率的沉积和蚀刻步骤顺序的高密度等离子体（HDP）沉积工艺来填充高纵横比间隙而无空隙形成的方法。 第一步使用小于1的蚀刻/剥离比快速填充间隙。 第一步在打开间隙之前中断。 第二步使用大于1的蚀刻/剥离比来扩大间隙。 在形成间隙的元件的角部暴露之前停止第二步骤。 可以重复这些步骤，直到间隙的纵横比减小，使得无空隙间隙填充成为可能。 可以优化每个步骤的蚀刻/剥离比和持续时间，以实现高通量和高纵横比填充间隙。

    Apparatus for chemical vapor deposition of aluminum oxide
    10.
    发明授权
    Apparatus for chemical vapor deposition of aluminum oxide 失效
    氧化铝化学气相沉积装置

    公开(公告)号：US5614247A

    公开(公告)日：1997-03-25

    申请号：US316303

    申请日：1994-09-30

    申请人： Steven G. Barbee ,  Richard A. Conti ,  Alexander Kostenko ,  Narayana V. Sarma ,  Donald L. Wilson ,  Justin W. Wong ,  Steven P. Zuhoski

    发明人： Steven G. Barbee ,  Richard A. Conti ,  Alexander Kostenko ,  Narayana V. Sarma ,  Donald L. Wilson ,  Justin W. Wong ,  Steven P. Zuhoski

    IPC分类号： C23C16/40 ,  C23C16/46 ,  C23C16/52 ,  H01L21/205 ,  H01L21/31

    CPC分类号： C23C16/403 ,  C23C16/46 ,  C23C16/52

    摘要： An apparatus in a chemical vapor deposition (CVD) system monitors the actual wafer/substrate temperature during the deposition process. The apparatus makes possible the production of high quality aluminum oxide films with real-time wafer/substrate control. An infrared (IR) temperature monitoring device is used to control the actual wafer temperature to the process temperature setpoint. This eliminates all atmospheric temperature probing. The need for test runs and monitor waters as well as the resources required to perform the operations is eliminated and operating cost are reduced. High quality, uniform films of aluminum oxide can be deposited on a silicon substrates with no need for additional photolithographic steps to simulate conformality that are present in a sputtered (PVD) type application. The result is a reduction in required process steps with subsequent anticipated savings in equipment, cycle time, chemicals, reduce handling, and increased yield of devices on the substrate. The apparatus incorporates a heated source material, heated delivery lines, heated inert gas purge lines, a pressure differential mass flow controller, a control system with related valving, and a vacuum process chamber with walls that are temperature controlled as a complete source delivery system to accurately and repeatably provide source vapor for LPCVD deposition of aluminum oxide onto silicon substrates.

    摘要翻译： 化学气相沉积（CVD）系统中的装置在沉积过程中监测实际的晶片/衬底温度。 该设备使得可以生产具有实时晶片/衬底控制的高品质氧化铝膜。 使用红外（IR）温度监测装置将实际晶片温度控制到过程温度设定值。 这消除了所有的大气温度探测。 测试运行和监控水的需求以及执行操作所需的资源被消除，运行成本降低。 可以在硅衬底上沉积高质量均匀的氧化铝膜，而不需要额外的光刻步骤来模拟存在于溅射（PVD）型应用中的共形性。 结果是所需的工艺步骤减少，随后预期节省设备，循环时间，化学品，减少处理和提高基材上装置的产量。 该装置包括加热的源材料，加热的输送管线，加热的惰性气体吹扫管线，压差质量流量控制器，具有相关阀门的控制系统和具有作为完整源输送系统温度控制的壁的真空处理室 准确并重复地提供源蒸气，用于LPCVD在硅衬底上沉积氧化铝。