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1.发明申请Structure and method for creating reliable via contacts for interconnect applications 有权用于为互连应用创建可靠的通孔触点的结构和方法公开(公告)号：US20070267751A1
公开(公告)日：2007-11-22
申请号：US11435410
申请日：2006-05-17
IPC分类号： H01L23/52
CPC分类号： H01L21/76834 , H01L21/288 , H01L21/76814 , H01L21/76816 , H01L21/76843 , H01L21/76846 , H01L21/76852 , H01L2924/0002 , H01L2924/00
摘要： A reliable and mechanical strong interconnect structure is provided that does not include gouging features in the bottom of the an opening, particularly at a via bottom. Instead, the interconnect structures of the present invention utilize a Co-containing buffer layer that is selectively deposited on exposed surfaces of the conductive features that are located in a lower interconnect level. The selective deposition is performed through at least one opening that is present in a dielectric material of an upper interconnect level. The selective deposition is performed by electroplating or electroless plating. The Co-containing buffer layer comprises Co and at least one of P and B. W may optionally be also present in the Co-containing buffer layer.
摘要翻译： 提供了可靠和机械强的互连结构，其不包括开口底部的特别是在通孔底部的气泡特征。 相反，本发明的互连结构利用选择性地沉积在位于较低互连级别的导电特征的暴露表面上的含Co缓冲层。 选择性沉积通过存在于上部互连电平的电介质材料中的至少一个开口进行。 选择性沉积通过电镀或无电镀进行。 含Co缓冲层包含Co和P和B中的至少一个.W可选地也可以存在于含Co缓冲层中。
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2.发明授权Interconnect structure containing non-damaged dielectric and a via gouging feature 失效互连结构包含未损坏的电介质和通孔沟槽功能公开(公告)号：US08664766B2
公开(公告)日：2014-03-04
申请号：US12430436
申请日：2009-04-27
IPC分类号： H01L23/48
CPC分类号： H01L21/76831 , H01L21/02063 , H01L21/31105 , H01L21/31144 , H01L21/32131 , H01L21/76805 , H01L21/76808 , H01L21/76814 , H01L21/76843 , H01L21/76844 , H01L21/76873 , H01L23/5226 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure including a gouging feature at the bottom of one of the via openings. The structure includes an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein. The conductively filled via is in contact with an exposed surface of the at least one conductive feature of a first interconnect level by an anchoring area. The conductively filled via is separated from the second dielectric material by a first diffusion barrier layer, and the conductively filled line is separated from the second dielectric material by a second continuous diffusion barrier layer thereby the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line.
摘要翻译： 一种互连结构，包括在一个通孔开口的底部的气流特征。 该结构包括上部互连层，其包括具有至少一个导电填充通孔的第二电介质材料和布置在其中的上覆导电填充线。 导电填充的通孔通过锚固区域与第一互连水平的至少一个导电特征的暴露表面接触。 通过第一扩散阻挡层将导电填充的通孔与第二介电材料分离，并且通过第二连续扩散阻挡层将导电填充线与第二介电材料分离，由此第二介电材料在邻近的区域中不包括受损区域 导线填充线。
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3.发明申请METHOD OF PE-ALD OF SiNxCy AND INTEGRATION OF LINER MATERIALS ON POROUS LOW K SUBSTRATES 审中-公开SiNxCy的PE-AlD方法和多孔低K基体上衬层材料的整合公开(公告)号：US20120301706A1
公开(公告)日：2012-11-29
申请号：US13568808
申请日：2012-08-07
申请人： Andrew J. Kellock , Hyungjun Kim , Dae-Gyu Park , Satyanarayana V. Nitta , Sampath Purushothaman , Stephen Rossnagel , Oscar Van Der Straten
发明人： Andrew J. Kellock , Hyungjun Kim , Dae-Gyu Park , Satyanarayana V. Nitta , Sampath Purushothaman , Stephen Rossnagel , Oscar Van Der Straten
CPC分类号： C23C16/45536 , C23C16/36 , H01L21/02126 , H01L21/02167 , H01L21/0217 , H01L21/022 , H01L21/02203 , H01L21/02219 , H01L21/02274 , H01L21/0228 , H01L21/02315 , H01L21/3141 , H01L21/3148 , H01L21/31695 , H01L21/3185 , H01L21/76826 , H01L21/76831 , Y10T428/24999
摘要： A method of depositing a SiNxCy liner on a porous low thermal conductivity (low-k) substrate by plasma-enhanced atomic layer deposition (PE-ALD), which includes forming a SiNxCy liner on a surface of a low-k substrate having pores on a surface thereon, in which the low-k substrate is repeatedly exposed to a aminosilane-based precursor and a plasma selected from nitrogen, hydrogen, oxygen, helium, and combinations thereof until a thickness of the liner is obtained, and wherein the liner is prevented from penetrating inside the pores of a surface of the substrate. A porous low thermal conductivity substrate having a SiNxCy liner formed thereon by the method is also disclosed.
摘要翻译： 一种通过等离子体增强原子层沉积（PE-ALD）在多孔低热导率（低k）衬底上沉积SiNxCy衬垫的方法，其包括在具有孔的低k衬底的表面上形成SiN xCy衬垫 其中低k衬底反复暴露于基于氨基硅烷的前体和选自氮，氢，氧，氦及其组合的等离子体，直到获得衬垫的厚度，并且其中衬垫是 防止在基板的表面的孔内渗透。 还公开了通过该方法在其上形成SiN xCy衬垫的多孔低热导率衬底。
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4.发明申请STRUCTURE AND METHOD FOR CREATING RELIABLE VIA CONTACTS FOR INTERCONNECT APPLICATIONS 有权用于创建可靠联系的互连应用的结构和方法公开(公告)号：US20090298280A1
公开(公告)日：2009-12-03
申请号：US12538772
申请日：2009-08-10
IPC分类号： H01L21/768
CPC分类号： H01L21/76834 , H01L21/288 , H01L21/76814 , H01L21/76816 , H01L21/76843 , H01L21/76846 , H01L21/76852 , H01L2924/0002 , H01L2924/00
摘要： A reliable and mechanical strong interconnect structure is provided that does not include gouging features in the bottom of the an opening, particularly at a via bottom. Instead, the interconnect structures of the present invention utilize a Co-containing buffer layer that is selectively deposited on exposed surfaces of the conductive features that are located in a lower interconnect level. The selective deposition is performed through at least one opening that is present in a dielectric material of an upper interconnect level. The selective deposition is performed by electroplating or electroless plating. The Co-containing buffer layer comprises Co and at least one of P and B. W may optionally be also present in the Co-containing buffer layer.
摘要翻译： 提供了可靠和机械强的互连结构，其不包括开口底部的特别是在通孔底部的气泡特征。 相反，本发明的互连结构利用选择性地沉积在位于较低互连级别的导电特征的暴露表面上的含Co缓冲层。 选择性沉积通过存在于上部互连电平的电介质材料中的至少一个开口进行。 选择性沉积通过电镀或无电镀进行。 含Co缓冲层包含Co和P和B中的至少一个.W可选地也可以存在于含Co缓冲层中。
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公开(公告)号：US07800228B2
公开(公告)日：2010-09-21
申请号：US11435410
申请日：2006-05-17
IPC分类号： H01L23/52
CPC分类号： H01L21/76834 , H01L21/288 , H01L21/76814 , H01L21/76816 , H01L21/76843 , H01L21/76846 , H01L21/76852 , H01L2924/0002 , H01L2924/00
摘要： A reliable and mechanical strong interconnect structure is provided that does not include gouging features in the bottom of the an opening, particularly at a via bottom. Instead, the interconnect structures of the present invention utilize a Co-containing buffer layer that is selectively deposited on exposed surfaces of the conductive features that are located in a lower interconnect level. The selective deposition is performed through at least one opening that is present in a dielectric material of an upper interconnect level. The selective deposition is performed by electroplating or electroless plating. The Co-containing buffer layer comprises Co and at least one of P and B. W may optionally be also present in the Co-containing buffer layer.
摘要翻译： 提供了可靠和机械强的互连结构，其不包括开口底部的特别是在通孔底部的气泡特征。 相反，本发明的互连结构利用选择性地沉积在位于较低互连级别的导电特征的暴露表面上的含Co缓冲层。 选择性沉积通过存在于上部互连电平的电介质材料中的至少一个开口进行。 选择性沉积通过电镀或无电镀进行。 含Co缓冲层包含Co和P和B中的至少一个.W可选地也可以存在于含Co缓冲层中。
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公开(公告)号：US08835326B2
公开(公告)日：2014-09-16
申请号：US13343190
申请日：2012-01-04
申请人： John A. Fitzsimmons , Shyng-Tsong Chen , David L. Rath , Muthumanickam Sankarapandian , Oscar van der Straten
发明人： John A. Fitzsimmons , Shyng-Tsong Chen , David L. Rath , Muthumanickam Sankarapandian , Oscar van der Straten
IPC分类号： H01L21/3065 , H01L21/3213 , H01L21/02
CPC分类号： C09K13/00 , H01L21/02063 , H01L21/31144 , H01L21/32134 , H01L21/76802 , H01L21/76804
摘要： A chemical solution that removes undesired metal hard mask yet remains selective to the device wiring metallurgy and dielectric materials. The present invention decreases aspect ratio by selective removal of the metal hard mask before the metallization of the receiving structures without adverse damage to any existing metal or dielectric materials required to define the semiconductor device, e.g. copper metallurgy or device dielectric. Thus, an improved aspect ratio for metal fill without introducing any excessive trapezoidal cross-sectional character to the defined metal receiving structures of the device will result.
摘要翻译： 一种去除不需要的金属硬掩模的化学溶液，但仍然对器件布线冶金和电介质材料具有选择性。 本发明通过在接收结构金属化之前选择性去除金属硬掩模而不损害限定半导体器件所需的任何现有金属或介电材料，从而降低纵横比，例如， 铜冶金或器件电介质。 因此，将导致金属填充物的改进的纵横比，而不会对设备的限定的金属接收结构引入任何过大的梯形横截面特征。
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公开(公告)号：US20090206485A1
公开(公告)日：2009-08-20
申请号：US12430436
申请日：2009-04-27
IPC分类号： H01L23/532 , H01L23/48
CPC分类号： H01L21/76831 , H01L21/02063 , H01L21/31105 , H01L21/31144 , H01L21/32131 , H01L21/76805 , H01L21/76808 , H01L21/76814 , H01L21/76843 , H01L21/76844 , H01L21/76873 , H01L23/5226 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure including a gouging feature at the bottom of one of the via openings and a method of forming the same are provided. In accordance with the present invention, the method of forming the interconnect structure does not disrupt the coverage of the deposited diffusion barrier in the overlying line opening, nor does it introduce damages caused by Ar sputtering into the dielectric material including the via and line openings. In accordance with the present invention, such an interconnect structure contains a diffusion barrier layer only within the via opening, but not in the overlying line opening. This feature enhances both mechanical strength and diffusion property around the via opening areas without decreasing volume fraction of conductor inside the line openings. In accordance with the present invention, such an interconnect structure is achieved by providing the gouging feature in the bottom of the via opening prior to formation of the line opening and deposition of the diffusion barrier in said line opening.
摘要翻译： 提供一种互连结构，其包括在一个通孔开口的底部的气泡特征及其形成方法。 根据本发明，形成互连结构的方法不会破坏上覆线路开口中沉积的扩散阻挡层的覆盖，也不会引起由Ar溅射引起的包括通孔和线路开口的电介质材料的损伤。 根据本发明，这种互连结构仅在通孔开口内包含扩散阻挡层，但不包括在上覆开口中。 该特征增强了通孔开口区域周围的机械强度和扩散性能，而不会降低线路开口内导体的体积分数。 根据本发明，这种互连结构是通过在形成线路开口和在所述线路开口中的扩散阻挡层的沉积之前提供通孔开口的底部中的气流特征来实现的。
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8.发明授权公开(公告)号：US07405153B2
公开(公告)日：2008-07-29
申请号：US11306932
申请日：2006-01-17
申请人： Sandra G. Malhotra , Hariklia Deligianni , Stephen M. Rossnagel , Xiaoyan Shao , Tsong-Lin Tai , Oscar van der Straten
发明人： Sandra G. Malhotra , Hariklia Deligianni , Stephen M. Rossnagel , Xiaoyan Shao , Tsong-Lin Tai , Oscar van der Straten
CPC分类号： H01L21/76843 , H01L21/28562 , H01L21/76861 , H01L21/76862 , H01L21/76873 , Y10S438/952
摘要： A process for the formation of an interconnect in a semiconductor structure including the steps of forming a dielectric layer on a substrate, forming a first barrier layer on the dielectric layer, forming a second barrier layer on the first barrier layer, wherein the second barrier layer is selected from the group consisting of ruthenium, platinum, palladium, rhodium and iridium and wherein the formation of the second barrier layer is manipulated so that the bulk concentration of oxygen in the second barrier layer is 20 atomic percent or less, and forming a conductive layer on the second barrier layer. The process may additionally include a step of treating the second barrier to reduce the amount of oxide on the surface of the second barrier layer.
摘要翻译： 一种在半导体结构中形成互连的方法，包括以下步骤：在衬底上形成电介质层，在电介质层上形成第一阻挡层，在第一阻挡层上形成第二阻挡层，其中第二阻挡层 选自钌，铂，钯，铑和铱，并且其中操作第二阻挡层的形成，使得第二阻挡层中的氧的体积浓度为20原子％以下，并且形成导电 层在第二阻挡层上。 该方法可以另外包括处理第二阻挡层以减少第二阻挡层表面上的氧化物的量的步骤。
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公开(公告)号：US20130171829A1
公开(公告)日：2013-07-04
申请号：US13343190
申请日：2012-01-04
申请人： John A. Fitzsimmons , Shyng-Tsong Chen , David L. Rath , Muthumanickam Sankarapandian , Oscar van der Straten
发明人： John A. Fitzsimmons , Shyng-Tsong Chen , David L. Rath , Muthumanickam Sankarapandian , Oscar van der Straten
IPC分类号： H01L21/3065 , C11D7/60
CPC分类号： C09K13/00 , H01L21/02063 , H01L21/31144 , H01L21/32134 , H01L21/76802 , H01L21/76804
摘要： A chemical solution that removes undesired metal hard mask yet remains selective to the device wiring metallurgy and dielectric materials. The present invention decreases aspect ratio by selective removal of the metal hard mask before the metallization of the receiving structures without adverse damage to any existing metal or dielectric materials required to define the semiconductor device, e.g. copper metallurgy or device dielectric. Thus, an improved aspect ratio for metal fill without introducing any excessive trapezoidal cross-sectional character to the defined metal receiving structures of the device will result.
摘要翻译： 一种去除不需要的金属硬掩模的化学溶液，但仍然对器件布线冶金和电介质材料具有选择性。 本发明通过在接收结构金属化之前选择性去除金属硬掩模而不损害限定半导体器件所需的任何现有金属或介电材料，从而降低纵横比，例如， 铜冶金或器件电介质。 因此，将导致金属填充物的改进的纵横比，而不会对设备的限定的金属接收结构引入任何过大的梯形横截面特征。
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10.发明授权Structure and method for creating reliable via contacts for interconnect applications 有权用于为互连应用创建可靠的通孔触点的结构和方法公开(公告)号：US07960274B2
公开(公告)日：2011-06-14
申请号：US12538772
申请日：2009-08-10
IPC分类号： H01L21/768
CPC分类号： H01L21/76834 , H01L21/288 , H01L21/76814 , H01L21/76816 , H01L21/76843 , H01L21/76846 , H01L21/76852 , H01L2924/0002 , H01L2924/00
摘要： A reliable and mechanical strong interconnect structure is provided that does not include gouging features in the bottom of the an opening, particularly at a via bottom. Instead, the interconnect structures of the present invention utilize a Co-containing buffer layer that is selectively deposited on exposed surfaces of the conductive features that are located in a lower interconnect level. The selective deposition is performed through at least one opening that is present in a dielectric material of an upper interconnect level. The selective deposition is performed by electroplating or electroless plating. The Co-containing buffer layer comprises Co and at least one of P and B. W may optionally be also present in the Co-containing buffer layer.
摘要翻译： 提供了可靠和机械强的互连结构，其不包括开口底部的特别是在通孔底部的气泡特征。 相反，本发明的互连结构利用选择性地沉积在位于较低互连级别的导电特征的暴露表面上的含Co缓冲层。 选择性沉积通过存在于上部互连电平的电介质材料中的至少一个开口进行。 选择性沉积通过电镀或无电镀进行。 含Co缓冲层包含Co和P和B中的至少一个.W可选地也可以存在于含Co缓冲层中。
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