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    Method of making a floating gate non-volatile MOS semiconductor memory device with improved capacitive coupling
    2.
    发明授权
    Method of making a floating gate non-volatile MOS semiconductor memory device with improved capacitive coupling 有权
    制造具有改进的电容耦合的浮栅非易失性MOS半导体存储器件的方法

    公开(公告)号：US08384148B2

    公开(公告)日：2013-02-26

    申请号：US11317679

    申请日：2005-12-22

    申请人： Paolo Tessariol ,  Roberto Bez ,  Marcello Mariani

    发明人： Paolo Tessariol ,  Roberto Bez ,  Marcello Mariani

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A method of making a non-volatile MOS semiconductor memory device includes a formation step, in a semiconductor material substrate, of STI isolation regions (shallow trench isolation) filled by field oxide and of memory cells separated each other by said STI isolation regions. The memory cells include a gate electrode electrically isolated from said semiconductor material substrate by a first dielectric layer, and the gate electrode includes a floating gate self-aligned to the STI isolation regions. The method includes a formation phase of said floating gate exhibiting a substantially saddle shape including a concavity; the formation step of said floating gate includes a deposition step of a first conformal conductor material layer.

    摘要翻译： 一种制造非易失性MOS半导体存储器件的方法包括在半导体材料衬底中形成由场氧化物填充的STI隔离区（浅沟槽隔离）和由所述STI隔离区彼此分离的存储单元的形成步骤。 存储单元包括通过第一介电层与所述半导体材料基板电隔离的栅电极，并且所述栅电极包括与所述STI隔离区自对准的浮置栅极。 该方法包括所述浮动栅极的形成阶段，其显示包括凹面的基本上鞍形; 所述浮栅的形成步骤包括第一共形导体材料层的沉积步骤。

    Self-Aligned Bipolar Junction Transistors
    3.
    发明申请
    Self-Aligned Bipolar Junction Transistors 审中-公开
    自对准双极结晶体管

    公开(公告)号：US20110084247A1

    公开(公告)日：2011-04-14

    申请号：US12969652

    申请日：2010-12-16

    申请人： Fabio Pellizzer ,  Roberto Bez ,  Paola Zuliani ,  Augusto Benvenuti

    发明人： Fabio Pellizzer ,  Roberto Bez ,  Paola Zuliani ,  Augusto Benvenuti

    IPC分类号： H01L45/00 ,  H01L27/082

    CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L27/1022 ,  H01L27/24 ,  H01L29/66272

    摘要： A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second conduction regions and the control contact region. The second conduction regions may be formed by selectively implanting a first conductivity type dopant areas on a first side of selected silicide protection strips. The control contact region is formed by selectively implanting an opposite conductivity type dopant on a second side of the selected silicide protection strips.

    摘要翻译： 通过形成公共导电区域，在公共导电区域上的自身有效区域中延伸的多个控制区域，多个硅化物保护带和至少一个控制接触区域来形成多个双极晶体管。 在第二导电区域和控制接触区域上形成硅化物区域。 可以通过在所选择的硅化物保护条的第一侧选择性地注入第一导电类型的掺杂剂区域来形成第二导电区域。 通过在所选择的硅化物保护带的第二侧选择性地注入相反的导电型掺杂剂来形成控制接触区域。

    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array thereby manufactured
    4.
    发明授权
    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array thereby manufactured 有权
    因此制造Cu-damascene技术和相变存储器阵列中的相变存储器阵列的制造方法

    公开(公告)号：US07606056B2

    公开(公告)日：2009-10-20

    申请号：US11317622

    申请日：2005-12-22

    申请人： Fabio Pellizzer ,  Roberto Bez ,  Maria Santina Marangon ,  Roberta Piva ,  Laura Aina

    发明人： Fabio Pellizzer ,  Roberto Bez ,  Maria Santina Marangon ,  Roberta Piva ,  Laura Aina

    IPC分类号： G11C5/06

    CPC分类号： H01L45/1691 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    摘要： A process for manufacturing a phase change memory array includes the steps of: forming a plurality of phase change memory cells in an array region of a semiconductor wafer, the phase change memory cells arranged in rows and columns according to a row direction and to a column direction, respectively; forming a control circuit in a control region of the semiconductor wafer; forming a plurality of first bit line portions for mutually connecting phase change memory cells arranged on a same column; forming first level electrical interconnection structures; and forming second level electrical interconnection structures above the first level electrical interconnection structures. The first level electrical interconnection structures include second bit line portions laying on and in contact with the first bit line portions and projecting from the first bit line portions in the column direction for connecting the first bit line portions to the control circuit.

    摘要翻译： 一种相变存储器阵列的制造方法包括以下步骤：在半导体晶片的阵列区域中形成多个相变存储单元，根据行方向排列成行和列的相变存储单元和列 方向; 在所述半导体晶片的控制区域中形成控制电路; 形成多个第一位线部分，用于相互连接布置在同一列上的相变存储器单元; 形成一级电互连结构; 以及在所述第一级电互连结构之上形成第二级电互连结构。 第一级电互连结构包括布置在第一位线部分上并与第一位线部分接触的第二位线部分，并且在列方向上从第一位线部分突出以将第一位线部分连接到控制电路。

    Content addressable memory cell
    5.
    发明授权
    Content addressable memory cell 有权
    内容可寻址存储单元

    公开(公告)号：US07227765B2

    公开(公告)日：2007-06-05

    申请号：US10970842

    申请日：2004-10-20

    申请人： Guido De Sandre ,  Roberto Bez ,  Fabio Pellizzer

    发明人： Guido De Sandre ,  Roberto Bez ,  Fabio Pellizzer

    IPC分类号： G11C15/00

    CPC分类号： G11C15/04 ,  G11C13/0004 ,  G11C14/00 ,  G11C14/009 ,  G11C15/046

    摘要： A content addressable memory cell for a non-volatile content addressable memory, including a non-volatile storage element for storing a content digit, a selection input for selecting the memory cell, a search input for receiving a search digit, and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage element include at least one phase-change memory element for storing in a non-volatile way the respective content digit.

    摘要翻译： 一种用于非易失性内容可寻址存储器的内容可寻址存储器单元，包括用于存储内容数位的非易失性存储元件，用于选择存储单元的选择输入，用于接收搜索数字的搜索输入以及比较电路装置 用于将搜索数字与内容数字进行比较，并用于驱动存储器单元的匹配输出，以便发出内容数字和搜索数字之间的匹配。 非易失性存储元件包括用于以非易失性方式存储相应内容数字的至少一个相变存储器元件。

    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array manufactured thereby
    7.
    发明申请
    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array manufactured thereby 有权
    用于制造Cu-镶嵌技术中的相变存储器阵列的方法和由其制造的相变存储器阵列

    公开(公告)号：US20050064606A1

    公开(公告)日：2005-03-24

    申请号：US10902508

    申请日：2004-07-29

    申请人： Fabio Pellizzer ,  Roberto Bez

    发明人： Fabio Pellizzer ,  Roberto Bez

    IPC分类号： H01L27/24 ,  H01L21/00

    CPC分类号： H01L27/2472 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    摘要： A process for manufacturing a phase change memory array, includes the steps of: forming a plurality of PCM cells, arranged in rows and columns; and forming a plurality of resistive bit lines for connecting PCM cells arranged on a same column, each resistive bit lines comprising a respective phase change material portion, covered by a respective barrier portion. After forming the resistive bit lines, electrical connection structures for the resistive bit lines are formed directly in contact with the barrier portions of the resistive bit lines.

    摘要翻译： 一种制造相变存储器阵列的方法，包括以下步骤：形成以行和列排列的多个PCM单元; 以及形成用于连接布置在同一列上的PCM单元的多个电阻位线，每个电阻位线包括由相应的阻挡部分覆盖的各个相变材料部分。 在形成电阻位线之后，电阻位线的电连接结构直接形成为与电阻位线的势垒部分接触。

    Field programmable gate array device
    8.
    发明申请
    Field programmable gate array device 有权
    现场可编程门阵列器件

    公开(公告)号：US20050062497A1

    公开(公告)日：2005-03-24

    申请号：US10948079

    申请日：2004-09-23

    申请人： Fabio Pellizzer ,  Guido De Sandre ,  Roberto Bez

    发明人： Fabio Pellizzer ,  Guido De Sandre ,  Roberto Bez

    IPC分类号： G11C16/02 ,  G11C16/04 ,  H03K3/037 ,  H03K19/177

    CPC分类号： G11C13/0004 ,  G11C16/0416 ,  H03K3/0375 ,  H03K19/1776

    摘要： The present invention proposes a Field Programmable Gate Array device comprising a plurality of configurable electrical connections, a plurality of controlled switches, each one adapted to activating/de-activating at least one respective electrical connection in response to a switch control signal and a control unit including an arrangement of a plurality of control cells. Each control cells controls at least one of said controlled switches by the respective switch control signal, each control cell including a volatile storage element adapted to storing in a volatile way a control logic value corresponding to a preselected status of the at least one controlled switch, and providing to the controlled switch said switch control signal corresponding to the stored logic value. Each control cell further includes a non-volatile storage element coupled to the volatile storage element, the non-volatile storage element being adapted to storing in a non-volatile way the control logic value.

    摘要翻译： 本发明提出了一种现场可编程门阵列器件，其包括多个可配置的电连接，多个受控开关，每个控制开关适于响应于开关控制信号激活/去激活至少一个相应的电连接，控制单元 包括多个控制单元的布置。 每个控制单元通过相应的开关控制信号控制所述受控开关中的至少一个，每个控制单元包括易失性存储元件，其适于以易失性方式存储对应于至少一个受控开关的预选状态的控制逻辑值， 以及向受控开关提供与所存储的逻辑值对应的所述开关控制信号。 每个控制单元还包括耦合到易失性存储元件的非易失性存储元件，非易失性存储元件适于以非易失性方式存储控制逻辑值。

    High capacity capacitor and corresponding manufacturing process
    9.
    发明授权
    High capacity capacitor and corresponding manufacturing process 失效
    大容量电容器及相应的制造工艺

    公开(公告)号：US06222245B1

    公开(公告)日：2001-04-24

    申请号：US08739997

    申请日：1996-10-30

    申请人： Roberto Bez ,  Emilio Camerlenghi

    发明人： Roberto Bez ,  Emilio Camerlenghi

    IPC分类号： H01L2900

    CPC分类号： H01L28/40 ,  H01L29/94

    摘要： The invention relates to a high-capacitance capacitor which is monolithically integratable on a semiconductor substrate doped with a first type of dopant and accommodating a diffusion well which is doped with a second type of dopant and has a first active region formed therein. A layer of gate oxide is deposited over the diffusion well which is covered with a first layer of polycrystalline silicon and separated from a second layer of polycrystalline silicon by an interpoly dielectric layer. Advantageously, the high-capacitance capacitor of the invention includes a first elementary capacitor having the first and second layers of polycrystalline silicon as its conductive plates, and the interpoly dielectric layer as the isolation dielectric, and a second elementary capacitor having the first layer of polycrystalline silicon and the diffusion well as its conductive plates and the gate oxide layer as the isolation dielectric.

    摘要翻译： 本发明涉及一种高容量电容器，该高容量电容器可单独集成在掺杂有第一类掺杂剂的半导体衬底上，并且容纳掺杂有第二类掺杂剂的扩散阱，并且其中形成有第一有源区。 栅极氧化物沉积在扩散阱上，该扩散阱被第一多晶硅层覆盖，并通过多晶硅介电层与第二多晶硅层分离。有利的是，本发明的大容量电容器包括具有 第一和第二层多晶硅作为其导电板，并且作为隔离电介质的多晶硅绝缘层，以及具有第一层多晶硅和扩散阱作为其导电板的第二基本电容器，以及作为隔离层的栅极氧化物层 电介质。

    Method for erasing an electrically programmable and erasable non-volatile memory cell
    10.
    发明授权
    Method for erasing an electrically programmable and erasable non-volatile memory cell 失效
    擦除电可编程和可擦除非易失性存储单元的方法

    公开(公告)号：US5784319A

    公开(公告)日：1998-07-21

    申请号：US788530

    申请日：1997-01-24

    申请人： Corrado Villa ,  Roberto Bez ,  Daniele Cantarelli ,  Marco Dallabora

    发明人： Corrado Villa ,  Roberto Bez ,  Daniele Cantarelli ,  Marco Dallabora

    IPC分类号： G11C16/02 ,  G11C16/06 ,  G11C16/14

    CPC分类号： G11C16/14

    摘要： A method for erasing an electrically programmable and erasable non-volatile memory cell having a control electrode, an electrically-insulated electrode and a first electrode. The method provides for coupling the control electrode to a first voltage supply and coupling the first electrode to a second voltage supply. The first voltage supply and the second voltage supply are suitable to cause tunneling of electric charges between the electrically-insulated electrode and the first electrode. The method also provides for a constant current to flow between the second voltage supply and the first electrode of the memory cell for at least part of an erasing time of the memory cell, the constant current having a prescribed value.

    摘要翻译： 一种用于擦除具有控制电极，电绝缘电极和第一电极的电可编程和可擦除非易失性存储单元的方法。 该方法提供将控制电极耦合到第一电压源并将第一电极耦合到第二电压源。 第一电压源和第二电压源适于在电绝缘电极和第一电极之间引起电荷的隧穿。 该方法还提供恒定电流在存储器单元的第二电压源和第一电极之间流动，用于存储单元的擦除时间的至少一部分，恒定电流具有规定值。