公开(公告)号：US20060030133A1

公开(公告)日：2006-02-09

申请号：US11208359

申请日：2005-08-19

申请人： Paul Agnello ,  Stephen Bedell ,  Robert Dennard ,  Anthony Domenicucci ,  Keith Fogel ,  Devendra Sadana

发明人： Paul Agnello ,  Stephen Bedell ,  Robert Dennard ,  Anthony Domenicucci ,  Keith Fogel ,  Devendra Sadana

IPC分类号： H01L21/20 ,  H01L33/00 ,  H01L21/36

CPC分类号： H01L21/324 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66893 ,  H01L29/78603

摘要： Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.

摘要翻译： 提供形成基本上松弛和低缺陷的SGOI基底材料的热混合方法。 所述方法包括图形化步骤，其用于形成至少包含形成在Ge抗蚀扩散阻挡层顶上的SiGe岛的结构。 将SiGe层图案化成岛以这样的方式改变作用在每个岛边缘处的局部力，使得松弛力大于抵抗放松的力。 在图案化层的边缘处没有恢复力允许最终的SiGe膜比如果膜是连续的那样进一步松弛。

公开(公告)号：US20060081837A1

公开(公告)日：2006-04-20

申请号：US11293774

申请日：2005-12-02

申请人： Stephen Bedell ,  Anthony Domenicucci ,  Keith Fogel ,  Effendi Leobandung ,  Devendra Sadana

发明人： Stephen Bedell ,  Anthony Domenicucci ,  Keith Fogel ,  Effendi Leobandung ,  Devendra Sadana

IPC分类号： H01L31/109

CPC分类号： H01L29/78696 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02521 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/76251 ,  H01L29/7842

摘要： A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.

公开(公告)号：US20070105350A1

公开(公告)日：2007-05-10

申请号：US11619040

申请日：2007-01-02

申请人： Stephen Bedell ,  Huajie Chen ,  Anthony Domenicucci ,  Keith Fogel ,  Devendra Sadana

发明人： Stephen Bedell ,  Huajie Chen ,  Anthony Domenicucci ,  Keith Fogel ,  Devendra Sadana

IPC分类号： C30B1/00 ,  H01L21/20

CPC分类号： H01L21/7624 ,  Y10S438/933 ,  Y10T428/12674

摘要： A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.

摘要翻译： 描述了可以用作应变Si的模板的制造高质量，基本上松弛的绝缘体上硅衬底材料的方法。 使用具有非常薄的顶部Si层的绝缘体上硅衬底作为压缩应变SiGe生长的模板。 当SiGe层在足够的温度下弛豫时，位错运动的性质使得当埋入的氧化物半粘着时，应变消除缺陷向下移动到薄的Si层中。 薄Si层被掩埋氧化物/薄Si界面的氧化所消耗。 这可以通过在高温下使用内部氧化来实现。 以这种方式，原始薄Si层的作用是在SiGe合金的弛豫期间用作牺牲缺陷陷阱，SiGe合金随后可以使用内部氧化来消耗。

公开(公告)号：US20080116483A1

公开(公告)日：2008-05-22

申请号：US12027561

申请日：2008-02-07

申请人： Stephen Bedell ,  Huajie Chen ,  Anthony Domenicucci ,  Keith Fogel ,  Richard Murphy ,  Devendra Sadana

发明人： Stephen Bedell ,  Huajie Chen ,  Anthony Domenicucci ,  Keith Fogel ,  Richard Murphy ,  Devendra Sadana

IPC分类号： H01L29/165

CPC分类号： H01L21/26506 ,  H01L21/324 ,  H01L21/7624 ,  H01L21/76254 ,  H01L29/1054

摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.

摘要翻译： 提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。 该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。 然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓形成堆垛层错缺陷。 加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。 此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。 在一个实施方案中，加热步骤包括氧化过程，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。 该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。

公开(公告)号：US20050208780A1

公开(公告)日：2005-09-22

申请号：US11029921

申请日：2005-01-05

申请人： Stephen Bedell ,  Anthony Domenicucci ,  Keith Fogel ,  Devendra Sadana

发明人： Stephen Bedell ,  Anthony Domenicucci ,  Keith Fogel ,  Devendra Sadana

IPC分类号： C30B1/00 ,  H01L21/00 ,  H01L21/20 ,  H01L21/324 ,  H01L21/477 ,  H01L21/762 ,  H01L27/01

CPC分类号： H01L21/26506 ,  H01L21/324 ,  H01L21/7624 ,  H01L21/76254 ,  H01L29/1054

摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.

摘要翻译： 提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。 该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。 然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。 加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。 此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。

公开(公告)号：US20060001089A1

公开(公告)日：2006-01-05

申请号：US10883883

申请日：2004-07-02

申请人： Stephen Bedell ,  Anthony Domenicucci ,  Keith Fogel ,  Effendi Leobandung ,  Devendra Sadana

发明人： Stephen Bedell ,  Anthony Domenicucci ,  Keith Fogel ,  Effendi Leobandung ,  Devendra Sadana

IPC分类号： H01L31/0392 ,  H01L21/84

CPC分类号： H01L29/78696 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02521 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/76251 ,  H01L29/7842

摘要： A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.

摘要翻译： 提供了一种在绝缘层上形成包括第一应变半导体层的半导体结构的方法，其中第一应变半导体层相对较薄（小于约）并且具有低缺陷密度（堆垛层错和穿线缺陷）。 本发明的方法开始于在包括位于绝缘层顶部的第一半导体层的结构上形成应力提供层，例如SiGe合金层。 然后将应力提供层和第一半导体层图案化成至少一个岛，然后将含有至少一个岛的结构加热到使得应力转移从应力提供层到第一半导体层的温度。 在应变转移之后，将应力提供层从结构上去除，以形成直接位于所述绝缘层顶部的第一应变半导体岛层。

公开(公告)号：US20050003229A1

公开(公告)日：2005-01-06

申请号：US10610612

申请日：2003-07-01

申请人： Stephen Bedell ,  Huajie Chen ,  Anthony Domenicucci ,  Keith Fogel ,  Devendra Sadana

发明人： Stephen Bedell ,  Huajie Chen ,  Anthony Domenicucci ,  Keith Fogel ,  Devendra Sadana

IPC分类号： H01L27/12 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L21/425 ,  B32B15/00

CPC分类号： H01L21/7624 ,  Y10S438/933 ,  Y10T428/12674

摘要： A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.

摘要翻译： 描述了可以用作应变Si的模板的制造高质量，基本上松弛的绝缘体上硅衬底材料的方法。 使用具有非常薄的顶部Si层的绝缘体上硅衬底作为压缩应变SiGe生长的模板。 当SiGe层在足够的温度下弛豫时，位错运动的性质使得当埋入的氧化物半粘着时，应变消除缺陷向下移动到薄的Si层中。 薄Si层被掩埋氧化物/薄Si界面的氧化所消耗。 这可以通过在高温下使用内部氧化来实现。 以这种方式，原始薄Si层的作用是在SiGe合金的弛豫期间用作牺牲缺陷陷阱，SiGe合金随后可以使用内部氧化来消耗。

公开(公告)号：US20050045819A1

公开(公告)日：2005-03-03

申请号：US10604989

申请日：2003-08-29

申请人： Stephen Bedell ,  John Bruley ,  Anthony Domenicucci ,  Devendra Sadana

发明人： Stephen Bedell ,  John Bruley ,  Anthony Domenicucci ,  Devendra Sadana

IPC分类号： G01N1/28 ,  G01N23/04 ,  H01J37/26 ,  G01D18/00

CPC分类号： G01N23/04 ,  G01N2001/2893 ,  H01J37/261 ,  H01J2237/2826

摘要： A method and calibration standard for fabricating on a single substrate a series of crystalline pairs such that the d-spacing difference between the pairs will generate Moire fringes of the correct spacings to optimally calibrate the magnification settings of an electron microscope over a variety of magnification settings in the range of 5000× to 200,000×. The invention enables the tailoring of Moire fringe spacings to a desired magnification setting for calibration purposes by fabricating a series of patterns on a single substrate whereby each magnification setting is easily calibrated using a specific SGOI structure that is selected by a simple x-y translation across the top plan surface of the SGOI structure, therein eliminating the need for removing calibration samples in and out of the electron microscope. The method and calibration standard may be used for calibrating electron microscopes, such as, scanning transmission electron microscopes and transmission electron microscopes.

摘要翻译： 一种用于在单个基板上制造一系列晶体对的方法和校准标准，使得对之间的d间距差会产生正确间隔的莫尔条纹，以便通过各种放大设置最佳地校准电子显微镜的放大倍率设置 在5000x到200,000x的范围内。 通过在单个基板上制造一系列图案，本发明可以通过在单个基板上制造一系列图案来将莫尔条纹间距定制到所需的放大倍率设置，从而可以使用特定的SGOI结构轻松校准每个放大倍数设置，该SGOI结构通过顶部的简单xy平移 SGOI结构的平面表面，其中不需要将校准样品移入和移出电子显微镜。 该方法和校准标准可用于校准电子显微镜，例如扫描透射电子显微镜和透射电子显微镜。

公开(公告)号：US20070281439A1

公开(公告)日：2007-12-06

申请号：US11840389

申请日：2007-08-17

申请人： Stephen Bedell ,  Keith Fogel ,  Bruce Furman ,  Sampath Purushothaman ,  Devendra Sadana ,  Anna Topol

发明人： Stephen Bedell ,  Keith Fogel ,  Bruce Furman ,  Sampath Purushothaman ,  Devendra Sadana ,  Anna Topol

IPC分类号： H01L21/30 ,  H01L21/00

CPC分类号： H01L21/76259 ,  Y10T428/249961

摘要： Techniques for the fabrication of semiconductor devices are provided. In one aspect, a layer transfer structure is provided. The layer transfer structure comprises a carrier substrate having a porous region with a tuned porosity in combination with an implanted species defining a separation plane therein In another aspect, a method of forming a layer transfer structure is provided. In yet another aspect, a method of forming a thee dimensional integrated structure is provided.

摘要翻译： 提供了制造半导体器件的技术。 一方面，提供了层转移结构。 层转移结构包括具有调谐孔隙度的多孔区域的载体衬底以及限定分离平面的注入物质的组合。另一方面，提供了一种形成层转移结构的方法。 另一方面，提供了一种形成一维一体结构的方法。

公开(公告)号：US20070164356A1

公开(公告)日：2007-07-19

申请号：US11332564

申请日：2006-01-13

申请人： Thomas Adam ,  Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Thomas Adam ,  Stephen Bedell ,  Joel de Souza ,  Keith Fogel ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/76243 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78654

摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

摘要翻译： 提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。 通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。 在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。