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    Circuits and methods for lowering leakage in ultra-low-power MOS integrated circuits
    3.
    发明授权
    Circuits and methods for lowering leakage in ultra-low-power MOS integrated circuits 有权

    公开(公告)号：US10262985B2

    公开(公告)日：2019-04-16

    申请号：US15589975

    申请日：2017-05-08

    Applicant: Perceptia Devices, Inc.

    Inventor： Timothy Robins ,  Julian Jenkins

    IPC: G05F1/10 ,  G05F3/02 ,  H01L27/02 ,  H03K19/003 ,  H03K19/0948 ,  H01L27/11 ,  H03K19/00 ,  G05F3/20

    Abstract: A block of logic gates has MOS transistors whose body terminals are connected with a body voltage rail and whose source terminals are connected with a logic reference voltage rail. The logic reference voltage rail is connected to the body voltage rail via a resistor. The resistor creates a negative feedback loop for leakage currents that stabilizes a reverse body bias voltage and reduces the influence of temperature, voltage, and process variations.The block may be NMOS, PMOS, or CMOS. In the case of CMOS, there are two body voltage rails, powered by a voltage source, two logic reference voltage rails, and two resistors. The reverse body bias voltages over the two resistors may be stabilized by decoupling capacitors. The two resistors may be trimmable. The resistors may be calibrated such that leakage currents are at a minimum value and the logic gates can switch just fast enough.

    Fractional-N PLL with sleep modes
    5.
    发明授权
    Fractional-N PLL with sleep modes 有权

    公开(公告)号：US10348315B2

    公开(公告)日：2019-07-09

    申请号：US15795119

    申请日：2017-10-26

    Applicant: Perceptia Devices, Inc.

    Inventor： André Grouwstra ,  Julian Jenkins

    IPC: H03L7/14 ,  H03L7/197 ,  H03L7/091 ,  H03L7/087 ,  H03L7/08 ,  H03L7/085 ,  H03L7/093 ,  H03L7/099 ,  H03L7/181 ,  H03L7/23

    Abstract: A phase-locked loop (PLL) has an oscillator, a counter and a register to sample the oscillator phase as an integer number. A phase predictor uses a fractional-N frequency control word (FCW) to calculate a predicted phase as an integer number. The integer difference between the sampled phase and the predicted phase is used as loop filter input, to generate an oscillator control signal that adjusts the oscillator frequency. The phase predictor may provide noise shaping, for example via a MASH modulator. A first sleep mode control signal blocks a reference clock and feedback of the oscillator clock to the counter. It may also freeze loop filter parameters and block the output clock. A second sleep mode control signal may stop the oscillator.

    FRACTIONAL-N JITTER ATTENUATOR
    6.
    发明申请
    FRACTIONAL-N JITTER ATTENUATOR 有权

    公开(公告)号：US20180138915A1

    公开(公告)日：2018-05-17

    申请号：US15612982

    申请日：2017-06-02

    Applicant: Perceptia Devices, Inc.

    Inventor： Julian Jenkins ,  André Grouwstra

    IPC: H03L7/14 ,  H03L7/091 ,  H03L7/197

    CPC classification number: H03L7/14 ,  H03L7/0802 ,  H03L7/085 ,  H03L7/087 ,  H03L7/091 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/181 ,  H03L7/1976 ,  H03L7/235 ,  H03L2207/50

    Abstract: A phase-locked loop (PLL) has a primary loop (with a reference clock) and a secondary loop (with a stable reference clock). The secondary loop may include a fractional-N PLL, and may include a secondary loop filter, oscillator, output clock counter, and phase predictor using a rational secondary frequency control word (FCW). The primary loop has a register sampling the oscillator phase from the counter, and a phase predictor which uses a primary fractional-N FCW to calculate a predicted phase as an integer number. The primary loop forwards the integer difference between the sampled phase and the predicted phase to a primary loop filter, which outputs the secondary FCW. The primary loop filter has a much lower bandwidth than the secondary loop filter. The PLL may have multiple primary loops, with a hitless switching function. A primary loop may have sleep mode. The PLL may also provide an oscillator sleep function.

    Delay line
    8.
    发明授权
    Delay line 有权

    公开(公告)号：US10069482B2

    公开(公告)日：2018-09-04

    申请号：US15275018

    申请日：2016-09-23

    Applicant: Perceptia Devices, Inc.

    Inventor： Julian Jenkins

    IPC: G06F17/10 ,  G06G7/02 ,  H03H17/02 ,  H03H17/00 ,  H03H17/08

    Abstract: A delay line is constructed by combining a phase generator and a fabric. The phase generator splits a digital input signal in multiple incrementally delayed versions, which are input to the fabric. The fabric has an array of node filters. Inputs of filters in the first array column are inputs of the fabric. A node filter has a delay element and a cross-coupling element, whose output signals are added or subtracted to form a filter output signal. A node filter in a row is concatenated to the previous filter in the row through its delay element. Inputs of cross-coupling elements are connected to other array rows. Outputs of node filters form the outputs of the fabric. Delay times of delay elements and cross-coupling elements are nominally equal. Drive strengths of cross-coupling elements may be lower than drive strengths of delay elements.

    Fractional-N jitter attenuator
    9.
    发明授权
    Fractional-N jitter attenuator 有权

    公开(公告)号：US09991898B1

    公开(公告)日：2018-06-05

    申请号：US15612982

    申请日：2017-06-02

    Applicant: Perceptia Devices, Inc.

    Inventor： Julian Jenkins ,  André Grouwstra

    IPC: H03L7/06 ,  H03L7/14 ,  H03L7/091 ,  H03L7/197

    CPC classification number: H03L7/14 ,  H03L7/0802 ,  H03L7/085 ,  H03L7/087 ,  H03L7/091 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/181 ,  H03L7/1976 ,  H03L7/235 ,  H03L2207/50

    Abstract: A phase-locked loop (PLL) has a primary loop (with a reference clock) and a secondary loop (with a stable reference clock). The secondary loop may include a fractional-N PLL, and may include a secondary loop filter, oscillator, output clock counter, and phase predictor using a rational secondary frequency control word (FCW). The primary loop has a register sampling the oscillator phase from the counter, and a phase predictor which uses a primary fractional-N FCW to calculate a predicted phase as an integer number. The primary loop forwards the integer difference between the sampled phase and the predicted phase to a primary loop filter, which outputs the secondary FCW. The primary loop filter has a much lower bandwidth than the secondary loop filter. The PLL may have multiple primary loops, with a hitless switching function. A primary loop may have sleep mode. The PLL may also provide an oscillator sleep function.

    Delay Line
    10.
    发明申请
    Delay Line 审中-公开
    延迟线

    公开(公告)号：US20170040976A1

    公开(公告)日：2017-02-09

    申请号：US15275018

    申请日：2016-09-23

    Applicant: Perceptia Devices, Inc.

    Inventor： Julian Jenkins

    IPC: H03H17/02

    CPC classification number: H03H17/0248 ,  H03H17/0009 ,  H03H17/08

    Abstract: A delay line is constructed by combining a phase generator and a fabric. The phase generator splits a digital input signal in multiple incrementally delayed versions, which are input to the fabric. The fabric has an array of node filters. Inputs of filters in the first array column are inputs of the fabric. A node filter has a delay element and a cross-coupling element, whose output signals are added or subtracted to form a filter output signal. A node filter in a row is concatenated to the previous filter in the row through its delay element. Inputs of cross-coupling elements are connected to other array rows. Outputs of node filters form the outputs of the fabric. Delay times of delay elements and cross-coupling elements are nominally equal. Drive strengths of cross-coupling elements may be lower than drive strengths of delay elements.

    Abstract translation: 延迟线通过组合相位发生器和织物构成。 相位发生器以多个递增延迟版本分割数字输入信号，这些版本被输入到结构。 该结构具有一个节点过滤器阵列。 第一个数组列中的过滤器的输入是织物的输入。 节点滤波器具有延迟元件和交叉耦合元件，其输出信号被相加或相减以形成滤波器输出信号。 一行中的节点过滤器通过其延迟元素连接到行中的先前过滤器。 交叉耦合元件的输入连接到其他阵列行。 节点过滤器的输出形成了结构的输出。 延迟元件和交叉耦合元件的延迟时间在名义上相等。 交叉耦合元件的驱动强度可能低于延迟元件的驱动强度。

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