公开(公告)号：US20120061661A1

公开(公告)日：2012-03-15

申请号：US13089282

申请日：2011-04-18

申请人： Po-Tsun Liu ,  Yi-Teh Chou ,  Li-Feng Teng ,  Fu-Hai Li ,  Han-Ping D. Shieh ,  Wei-Ting Lin ,  Ming-Chin Hung ,  Chun-Ching Hsiao ,  Jiun-Jye Chang ,  Po-Lun Chen

发明人： Po-Tsun Liu ,  Yi-Teh Chou ,  Li-Feng Teng ,  Fu-Hai Li ,  Han-Ping D. Shieh ,  Wei-Ting Lin ,  Ming-Chin Hung ,  Chun-Ching Hsiao ,  Jiun-Jye Chang ,  Po-Lun Chen

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78696

摘要： A semiconductor structure and a fabricating method thereof are provided. The fabricating method includes forming a gate, a source, and a drain on a substrate and forming an oxide semiconductor material between the gate and the source and drain. The oxide semiconductor material is formed by performing a deposition process, and nitrogen gas is introduced before the deposition process is completely performed, so as to form oxide semiconductor nitride on the oxide semiconductor material.

摘要翻译： 提供半导体结构及其制造方法。 制造方法包括在衬底上形成栅极，源极和漏极，并在栅极和源极和漏极之间形成氧化物半导体材料。 通过进行沉积工艺形成氧化物半导体材料，并且在完成沉积工艺之前引入氮气，以在氧化物半导体材料上形成氧化物半导体氮化物。

公开(公告)号：US20070128857A1

公开(公告)日：2007-06-07

申请号：US11446205

申请日：2006-06-05

申请人： Shrane-Ning Jenq ,  Hung-Wei Li ,  Min-Sheng Chu ,  Chi-Chao Wan ,  Yung-Yun Wang ,  Po-Tsun Liu

发明人： Shrane-Ning Jenq ,  Hung-Wei Li ,  Min-Sheng Chu ,  Chi-Chao Wan ,  Yung-Yun Wang ,  Po-Tsun Liu

IPC分类号： H01L21/4763

CPC分类号： H01L21/2885 ,  C23C18/1605 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/38 ,  C25D3/38 ,  C25D5/022 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1292

摘要： A method for manufacturing copper wires on a substrate for a flat panel display device is disclosed. The method comprises following steps: providing a substrate; forming a seed layer on the surface; forming a patterned photoresist on the surface of the seed layer to expose a part of the seed layer; and plating a copper layer on the exposed part of the seed layer. As the copper layer is plated, an electrolyte solution comprises a sulfur-containing compound is used. The angle between the surface of the copper layer and the contact surface of the seed layer is greater than 0 degree and less than 90 degree. Through the method illustrated above, the film step-coverage in the following process can be improved, the generated voids in device can be reduced, the manufacturing steps can be simplified, and the complicated etching process can be avoided.

摘要翻译： 公开了一种在平板显示装置用基板上制造铜线的方法。 该方法包括以下步骤：提供衬底; 在表面上形成种子层; 在所述种子层的表面上形成图案化的光致抗蚀剂以暴露所述种子层的一部分; 并在种子层的暴露部分上镀覆铜层。 当铜层被镀覆时，使用包含含硫化合物的电解质溶液。 铜层的表面与种子层的接触面之间的角度大于0度且小于90度。 通过上述方法，可以改善以下工序中的膜阶梯覆盖，可以减少器件中产生的空隙，可以简化制造步骤，可以避免复杂的蚀刻工艺。

公开(公告)号：US06673661B1

公开(公告)日：2004-01-06

申请号：US10324965

申请日：2002-12-20

申请人： Chi-Wen Liu ,  Ting-Chang Chang ,  Po-Tsun Liu ,  Ying-Lang Wang

发明人： Chi-Wen Liu ,  Ting-Chang Chang ,  Po-Tsun Liu ,  Ying-Lang Wang

IPC分类号： H01L2184

CPC分类号： H01L29/6675 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78684

摘要： A method for fabricating a dual gate thin film transistor (TFT) device provides for forming a pair of source/drain layers self-aligned with respect to a first gate electrode and forming a second gate electrode self-aligned with respect to both the pair of source/drain layers and the first gate electrode. Thus, the dual gate TFT device is fabricated with enhanced alignment. In addition, the dual gate TFT device (or a single gate TFT device) may be fabricated with source/drain layers formed of a silicon-germanium alloy material, such as to provide the TFT device with enhanced performance with respect to a kink effect.

摘要翻译： 制造双栅极薄膜晶体管（TFT）器件的方法提供了形成相对于第一栅极电极自对准的一对源极/漏极层，并且形成相对于所述一对栅极电极自对准的第二栅电极 源极/漏极层和第一栅极电极。 因此，双栅极TFT器件被制造成具有增强的对准。 此外，双栅极TFT器件（或单栅极TFT器件）可以由硅 - 锗合金材料形成的源极/漏极层制造，以提供相对于扭结效应具有增强性能的TFT器件。

公开(公告)号：US06521547B1

公开(公告)日：2003-02-18

申请号：US09682479

申请日：2001-09-07

申请人： Ting-Chang Chang ,  Po-Tsun Liu ,  Yi-Shien Mor

发明人： Ting-Chang Chang ,  Po-Tsun Liu ,  Yi-Shien Mor

IPC分类号： H01L2131

CPC分类号： H01L21/3105 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/76802

摘要： A method of repairing a low dielectric constant (low k) material layer starts with coating a photoresist layer on the low k material layer on a semiconductor wafer. After transferring a pattern of the photoresist layer to the low k material layer, an oxygen plasma ashing process is performed to remove the photoresist layer. Finally, by contacting the low k material layer with a solution of alkyl silane comprising an alkyl group and halo substituent, Si—OH bonds formed in the low k layer during the oxygen plasma ashing process are removed so as to repair damage to the low k material layer caused by the oxygen plasma ashing process, and to enhance a surface of the low k material layer to a hydrophobic surface to prevent moisture adhering to the surface of the low k material layer.

摘要翻译： 修复低介电常数（低k）材料层的方法首先在半导体晶片上的低k材料层上涂覆光致抗蚀剂层。 在将光致抗蚀剂层的图案转印到低k材料层之​​后，进行氧等离子体灰化处理以除去光致抗蚀剂层。 最后，通过使低k材料层与包含烷基和卤素取代基的烷基硅烷的溶液接触，除去在氧等离子体灰化过程中在低k层中形成的Si-OH键，以修复对低k 由氧等离子体灰化过程引起的材料层，并且将低k材料层的表面增强到疏水表面以防止水分粘附到低k材料层的表面。

公开(公告)号：US08563974B2

公开(公告)日：2013-10-22

申请号：US13195650

申请日：2011-08-01

申请人： Po-Tsun Liu ,  Yi-Teh Chou ,  Li-Feng Teng ,  Chur-Shyang Fu ,  Han-Ping Shieh

发明人： Po-Tsun Liu ,  Yi-Teh Chou ,  Li-Feng Teng ,  Chur-Shyang Fu ,  Han-Ping Shieh

IPC分类号： H01L29/10

CPC分类号： H01L29/78696 ,  H01L27/1225 ,  H01L27/286 ,  H01L29/7869 ,  H01L51/0036

摘要： The present invention relates to a high gain complementary inverter with ambipolar thin film transistors and fabrication thereof, comprising: a gate layer, a silica layer, a first active layer, a first source, a first drain, a second active layer, a second source and a second drain for fabrication cost and complexity reduction.

摘要翻译： 本发明涉及一种具有双极性薄膜晶体管的高增益互补型逆变器及其制造方法，包括：栅极层，二氧化硅层，第一有源层，第一源极，第一漏极，第二有源层，第二源极 以及用于制造成本和复杂性降低的第二个漏极。

公开(公告)号：US20120313104A1

公开(公告)日：2012-12-13

申请号：US13267065

申请日：2011-10-06

申请人： Po-Tsun LIU ,  Li-Wei Chu ,  Guang-Ting Zheng

发明人： Po-Tsun LIU ,  Li-Wei Chu ,  Guang-Ting Zheng

IPC分类号： H01L33/08

CPC分类号： H01L27/1255 ,  G09G3/3659 ,  G09G2300/0842 ,  H01L33/08

摘要： The present invention provides an analog memory cell circuit for the LTPS TFT-LCD. The circuit comprises the first transistor, second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the capacitor. It comprises a plurality of operation period, wherein the transistors are controlled in accordance with the first scan signal, the second scan signal, and the third scan signal, the output signal is output in the opposite to the output jack.

摘要翻译： 本发明提供一种用于LTPS TFT-LCD的模拟存储单元电路。 该电路包括第一晶体管，第二晶体管，第三晶体管，第四晶体管，第五晶体管，第六晶体管，第七晶体管和电容器。 它包括多个操作周期，其中根据第一扫描信号，第二扫描信号和第三扫描信号来控制晶体管，输出信号与输出插孔相反地输出。

公开(公告)号：US07795683B2

公开(公告)日：2010-09-14

申请号：US11561898

申请日：2006-11-21

申请人： Chi-Lin Chen ,  Yu-Cheng Chen ,  Hsing-Hua Wu ,  Po-Tsun Liu

发明人： Chi-Lin Chen ,  Yu-Cheng Chen ,  Hsing-Hua Wu ,  Po-Tsun Liu

IPC分类号： H01L29/04

CPC分类号： H01L21/268 ,  H01L21/28008 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/66757 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78675 ,  H01L29/78696

摘要： A structure of a thin film transistor and a method for making the same are provided. The structure includes a strip-shaped silicon island, a gate, and a first and second ion doping regions. The strip-shaped silicon island is a thin film region with a predetermined long side and short side, and farther has a plurality of lateral grain boundaries substantially parallel to the short side of the silicon island. The gate is located over the silicon island and substantially parallel to the lateral grain boundaries. The first and second ion doping regions, used as source/drain regions of the TFT, are located at two sides along the long side of the island and substantially perpendicular to the gate.

摘要翻译： 提供薄膜晶体管的结构及其制造方法。 该结构包括条形硅岛，栅极以及第一和第二离子掺杂区域。 带状硅岛是具有预定的长边和短边的薄膜区域，并且还具有基本上平行于硅岛短边的多个横向晶界。 栅极位于硅岛上方并且基本上平行于横向晶界。 用作TFT的源极/漏极区域的第一和第二离子掺杂区域位于岛的长边的两侧并且基本上垂直于栅极。

公开(公告)号：US07701007B2

公开(公告)日：2010-04-20

申请号：US11393742

申请日：2006-03-31

申请人： Chi-Wen Chen ,  Ting-Chang Chang ,  Po-Tsun Liu ,  Kuo-Yu Huang ,  Jen-Chien Peng

发明人： Chi-Wen Chen ,  Ting-Chang Chang ,  Po-Tsun Liu ,  Kuo-Yu Huang ,  Jen-Chien Peng

IPC分类号： H01L27/12

CPC分类号： H01L29/66765 ,  H01L27/124 ,  H01L27/1248

摘要： A Thin Film Transistor comprises a gate electrode formed on a substrate; a gate insulation layer covering the gate electrode; an amorphous silicon (a-Si) region disposed on the gate insulation layer and above the gate electrode; a doped a-Si region formed on the a-Si region; the source and drain metal regions separately formed on the doped a-Si region and above the gate electrode, and isolated from the a-Si region; a passivation layer formed on the gate insulation layer and covering the source, drain and data-line (DL) metal regions; and a conductive layer formed on the passivation layer. The passivation layer has a first, second and third vias for respectively exposing the partial surfaces of the source, drain and DL metal regions. The first, second and third vias are filled with the conductive layer, so that the DL and source metal regions are connected via the conductive layer.

摘要翻译： 薄膜晶体管包括形成在基板上的栅电极; 覆盖栅电极的栅极绝缘层; 设置在栅极绝缘层上和栅电极上方的非晶硅（a-Si）区; 形成在a-Si区上的掺杂a-Si区; 源极和漏极金属区域分别形成在掺杂的a-Si区域和栅电极上方，并与a-Si区域隔离; 形成在所述栅极绝缘层上并覆盖所述源极，漏极和数据线（DL）金属区域的钝化层; 以及形成在钝化层上的导电层。 钝化层具有用于分别暴露源极，漏极和DL金属区域的部分表面的第一，第二和第三通孔。 第一，第二和第三通孔填充有导电层，使得DL和源极金属区域经由导电层连接。

公开(公告)号：US07022571B2

公开(公告)日：2006-04-04

申请号：US10426873

申请日：2003-05-01

申请人： Ting-Chang Chang ,  Po-Tsun Liu

发明人： Ting-Chang Chang ,  Po-Tsun Liu

IPC分类号： H01L21/336

CPC分类号： H01L21/28185 ,  B82Y10/00 ,  H01L21/28194 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/517

摘要： A quantum structure and the forming method based on the difference in characteristic of two matters is provided. The forming method includes several steps. At first, providing a first dielectric layer for forming a second dielectric layer thereon. The second dielectric layer has major elements and impurities contained. Treating the second dielectric layer to drive the impurities to form the quantum structure. For example, oxidizing the major elements to drive the impurities in the first dielectric layer to form the quantum structure in said first dielectric layer because the oxidizing capability of the major elements is stronger than that of the impurities.

摘要翻译： 提供了基于两个特征的差异的量子结构和形成方法。 成型方法包括几个步骤。 首先，提供用于在其上形成第二电介质层的第一电介质层。 第二电介质层含有主要元素和杂质。 处理第二介质层以驱动杂质以形成量子结构。 例如，氧化主要元素以驱动第一电介质层中的杂质以在所述第一介电层中形成量子结构，因为主要元素的氧化能力比杂质的氧化能力更强。

公开(公告)号：US06423652B1

公开(公告)日：2002-07-23

申请号：US09420960

申请日：1999-10-19

申请人： Ting-Chang Chang ,  Po-Tsun Liu ,  Yi-Shien Mor

发明人： Ting-Chang Chang ,  Po-Tsun Liu ,  Yi-Shien Mor

IPC分类号： H01L2131

CPC分类号： H01L21/02137 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02351 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/3121

摘要： A post-processing treatment of a low dielectric constant material. In the post-processing treatment, a shallow implantation is conducted to form a shallow compact layer over a dielectric film. This shallow compact surface layer acts as a barrier that prevents the absorption of moisture by the dielectric film. The shallow implantation is carried out using boron ions at an energy level of between about 10 and 50 keV and a dosage of between about 1×1015 atm/cm2 and 1×1016 atm/cm2.

摘要翻译： 对低介电常数材料进行后处理处理。 在后处理处理中，进行浅注入以在电介质膜上形成浅致密层。 这种浅的紧密表面层用作防止电介质膜吸收水分的屏障。 在约10至50keV的能级和约1×10 15 atm / cm 2和1×10 16 atm / cm 2的剂量之间使用硼离子进行浅注入。