WIRING SUBSTRATE
    1.
    发明公开
    WIRING SUBSTRATE 审中-公开

    公开(公告)号:US20240324103A1

    公开(公告)日:2024-09-26

    申请号:US18613202

    申请日:2024-03-22

    申请人: IBIDEN CO., LTD.

    IPC分类号: H05K1/11 H05K1/03 H05K3/16

    摘要: A wiring substrate includes a core substrate including a through-hole conductor, a first resin insulating layer, a first conductor layer including a seed layer and an electrolytic plating layer, a via conductor formed such that the via conductor electrically connects the through-hole conductor and first conductor layer, and a second resin insulating layer covering the first conductor layer. The core substrate includes a glass substrate such that the through-hole conductor is penetrating through the glass substrate, the seed layer includes a first layer formed on the first resin insulating layer and a second layer formed on the first layer, and the first conductor layer includes a conductor circuit such that a width of the first layer is larger than a width of the second layer in the conductor circuit and a width of the electrolytic plating layer is larger than the width of the first layer in the conductor circuit.

    WIRING SUBSTRATE
    2.
    发明公开
    WIRING SUBSTRATE 审中-公开

    公开(公告)号:US20240306299A1

    公开(公告)日:2024-09-12

    申请号:US18595674

    申请日:2024-03-05

    申请人: IBIDEN CO., LTD.

    摘要: A wiring substrate includes a core substrate including a through-hole conductor, a resin insulating layer formed on the core substrate, a conductor layer formed on a surface of the resin insulating layer and including a seed layer and an electrolytic plating layer formed on the seed layer, and a via conductor formed in the resin insulating layer such that the via conductor is connected to the through-hole conductor in the core substrate and includes the seed layer and electrolytic plating layer extending from the conductor layer. The core substrate includes a glass substrate such that the through-hole conductor is formed in a through hole penetrating through the glass substrate, and the conductor layer and via conductor are formed such that the seed layer is formed by sputtering and includes an alloy including copper, aluminum, and one or more metals selected from nickel, zinc, gallium, silicon, and magnesium.

    PRINTED WIRING BOARD
    3.
    发明公开

    公开(公告)号:US20240260179A1

    公开(公告)日:2024-08-01

    申请号:US18426547

    申请日:2024-01-30

    申请人: IBIDEN CO., LTD.

    IPC分类号: H05K1/02 H05K1/05 H05K3/16

    摘要: A printed wiring board includes a conductor layer, an outermost insulating layer formed on the conductor layer and having an opening exposing a portion of the conductor layer, and a metal post formed in the opening of the outermost insulating layer and including a seed layer and an electrolytic plating layer formed on the seed layer such that the metal post has a height exceeding a surface of the outermost insulating layer and has a portion exceeding a height of the outermost insulating layer, the seed layer of the metal post has a first layer and a second layer formed on the first layer. The portion exceeding the height of the outermost insulating layer is formed such that a width of the first layer is larger than a width of the second layer, and a width of the electrolytic plating layer is larger than the width of the first layer.