利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

157 条记录 (耗时 0.02 秒)

    Method for fabricating a semiconductor test probe card space transformer
    3.
    发明授权
    Method for fabricating a semiconductor test probe card space transformer 有权
    制造半导体测试探针卡空间变压器的方法

    公开(公告)号：US08322020B2

    公开(公告)日：2012-12-04

    申请号：US13227580

    申请日：2011-09-08

    申请人： Ming Cheng Hsu ,  Clinton Chih-Chieh Chao

    发明人： Ming Cheng Hsu ,  Clinton Chih-Chieh Chao

    IPC分类号： H01F7/06

    CPC分类号： H05K3/243 ,  G01R1/07378 ,  G01R3/00 ,  G01R31/2863 ,  H05K3/108 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/049 ,  H05K2203/0542 ,  H05K2203/0574 ,  Y10T29/49004 ,  Y10T29/4902 ,  Y10T29/49036 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49162 ,  Y10T29/49167 ,  Y10T29/49169 ,  Y10T29/49204

    摘要： A space transformer for a semiconductor test probe card and method of fabrication. The method may include depositing a first metal layer as a ground plane on a space transformer substrate having a plurality of first contact test pads defining a first pitch spacing, depositing a first dielectric layer on the ground plane, forming a plurality of second test contacts defining a second pitch spacing different than the first pitch spacing, and forming a plurality of redistribution leads on the first dielectric layer to electrically couple the first contact test pads to the second contact test pads. In some embodiments, the redistribution leads may be built directly on the space transformer substrate. The method may be used in one embodiment to remanufacture an existing space transformer to produce fine pitch test pads having a pitch spacing smaller than the original test pads.

    摘要翻译： 一种用于半导体测试探针卡的空间变压器及其制造方法。 该方法可以包括在具有限定第一间距间隔的多个第一接触测试焊盘的空间变压器基板上沉积第一金属层作为接地平面，在接地平面上沉积第一介电层，形成多个第二测试触点， 与所述第一间距间隔不同的第二间距间隔，以及在所述第一介电层上形成多个再分配引线，以将所述第一接触测试焊盘电耦合到所述第二接触测试焊盘。 在一些实施例中，再分配引线可以直接构建在空间变换器基板上。 该方法可以在一个实施例中用于重新制造现有空间变压器以产生具有小于原始测试焊盘的间距间距的细间距测试焊盘。

    Method of manufacturing a printed circuit board (PCB)
    4.
    发明授权
    Method of manufacturing a printed circuit board (PCB) 有权
    制造印刷电路板（PCB）的方法

    公开(公告)号：US08122599B2

    公开(公告)日：2012-02-28

    申请号：US12288740

    申请日：2008-10-23

    申请人： Jae-Chul Ryu

    发明人： Jae-Chul Ryu

    IPC分类号： H05K3/02 ,  H05K1/00

    CPC分类号： H05K3/242 ,  H01L2924/0002 ,  H05K2203/0315 ,  H05K2203/0361 ,  H05K2203/0542 ,  H05K2203/1142 ,  H05K2203/1476 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49213 ,  H01L2924/00

    摘要： A printed circuit board (PCB) and appertaining method of manufacturing are provided. The method includes: coating a metal layer on the entire surface of a substrate having an outer surface on which an interconnection pattern is formed; partially removing the metal layer from the surface of the substrate to form a window for a chip to be mounted therein and partially exposing the interconnection pattern to form a bonding finger; forming a first insulating layer on the metal layer by primarily anodizing the metal layer; electroplating a surface of the bonding finger by supplying power to the metal layer; and forming a second insulating layer disposed below the first insulating layer by entirely and secondarily anodizing the metal layer. A gold electroplating process can be performed without a lead wire, and an oxide layer formed by an anodizing process can protect circuits formed on the substrate and electrically insulate them.

    摘要翻译： 提供印刷电路板（PCB）和制造方法。 该方法包括：在具有形成有互连图案的外表面的基板的整个表面上涂覆金属层; 从衬底的表面部分地去除金属层以形成用于芯片的窗口以安装在其中并部分地暴露互连图案以形成接合指状物; 通过主要阳极氧化金属层在金属层上形成第一绝缘层; 通过向金属层供电来对接合手指的表面进行电镀; 以及通过完全二次阳极氧化所述金属层来形成设置在所述第一绝缘层下方的第二绝缘层。 可以在没有引线的情况下进行金电镀工艺，并且通过阳极氧化工艺形成的氧化物层可以保护形成在基板上的电路并将其电绝缘。

    Method for fabricating a semiconductor test probe card space transformer
    5.
    发明授权
    Method for fabricating a semiconductor test probe card space transformer 有权
    制造半导体测试探针卡空间变压器的方法

    公开(公告)号：US08033012B2

    公开(公告)日：2011-10-11

    申请号：US12165970

    申请日：2008-07-01

    申请人： Ming Cheng Hsu ,  Clinton Chih-Chieh Chao

    发明人： Ming Cheng Hsu ,  Clinton Chih-Chieh Chao

    IPC分类号： H05K3/30

    CPC分类号： H05K3/243 ,  G01R1/07378 ,  G01R3/00 ,  G01R31/2863 ,  H05K3/108 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/049 ,  H05K2203/0542 ,  H05K2203/0574 ,  Y10T29/49004 ,  Y10T29/4902 ,  Y10T29/49036 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49162 ,  Y10T29/49167 ,  Y10T29/49169 ,  Y10T29/49204

    摘要： A space transformer for a semiconductor test probe card and method of fabrication. The method may include depositing a first metal layer as a ground plane on a space transformer substrate having a plurality of first contact test pads defining a first pitch spacing, depositing a first dielectric layer on the ground plane, forming a plurality of second test contacts defining a second pitch spacing different than the first pitch spacing, and forming a plurality of redistribution leads on the first dielectric layer to electrically couple the first contact test pads to the second contact test pads. In some embodiments, the redistribution leads may be built directly on the space transformer substrate. The method may be used in one embodiment to remanufacture an existing space transformer to produce fine pitch test pads having a pitch spacing smaller than the original test pads. In some embodiments, the test pads may be C4 test pads.

    摘要翻译： 一种用于半导体测试探针卡的空间变压器及其制造方法。 该方法可以包括在具有限定第一间距间隔的多个第一接触测试焊盘的空间变压器基板上沉积第一金属层作为接地平面，在接地平面上沉积第一介电层，形成多个第二测试触点， 与所述第一间距间隔不同的第二间距间隔，以及在所述第一介电层上形成多个再分配引线，以将所述第一接触测试焊盘电耦合到所述第二接触测试焊盘。 在一些实施例中，再分配引线可以直接构建在空间变换器基板上。 该方法可以在一个实施例中用于重新制造现有空间变压器以产生具有小于原始测试焊盘的间距间距的细间距测试焊盘。 在一些实施例中，测试焊盘可以是C4测试焊盘。

    Insulation structure for high temperature conditions and manufacturing method thereof
    6.
    发明授权
    Insulation structure for high temperature conditions and manufacturing method thereof 有权
    高温条件的绝缘结构及其制造方法

    公开(公告)号：US07998879B2

    公开(公告)日：2011-08-16

    申请号：US11723236

    申请日：2007-03-19

    申请人： Young Ki Lee ,  Seog Moon Choi ,  Sang Hyun Shin

    发明人： Young Ki Lee ,  Seog Moon Choi ,  Sang Hyun Shin

    IPC分类号： H01L21/31

    CPC分类号： H01L33/486 ,  H01L33/60 ,  H01L33/62 ,  H05K3/28 ,  H05K2203/0315 ,  H05K2203/0542

    摘要： An insulation structure for high temperature conditions and a manufacturing method thereof. In the insulation structure, a substrate has a conductive pattern formed on at least one surface thereof for electrical connection of a device. A metal oxide layer pattern is formed on a predetermined portion of the conductive pattern by anodization, the metal oxide layer pattern made of one selected from a group consisting of Al, Ti and Mg.

    摘要翻译： 一种用于高温条件的绝缘结构及其制造方法。 在绝缘结构中，衬底具有形成在其至少一个表面上的用于电连接器件的导电图案。 通过阳极氧化在导电图案的预定部分上形成金属氧化物层图案，金属氧化物层图案由选自Al，Ti和Mg的一种形成。

    Multilayer substrate and manufacturing method thereof
    7.
    发明授权
    Multilayer substrate and manufacturing method thereof 有权
    多层基板及其制造方法

    公开(公告)号：US07868464B2

    公开(公告)日：2011-01-11

    申请号：US11229394

    申请日：2005-09-15

    申请人： Kenichi Kawabata ,  Hisayuki Abe ,  Masashi Katsumata

    发明人： Kenichi Kawabata ,  Hisayuki Abe ,  Masashi Katsumata

    IPC分类号： H01L23/485

    CPC分类号： H05K1/0265 ,  C25D5/022 ,  H05K3/0032 ,  H05K3/06 ,  H05K3/064 ,  H05K3/107 ,  H05K3/108 ,  H05K3/20 ,  H05K3/243 ,  H05K3/421 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0376 ,  H05K2201/0394 ,  H05K2201/09036 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2203/0384 ,  H05K2203/0542 ,  H05K2203/1476 ,  Y10T428/24917

    摘要： A multilayer substrate according to the present invention includes a plurality of laminated insulating layers and conductive patterns formed between the respective insulating layers. The conductive patterns include a first conductive pattern having a predetermined thickness and a second conductive pattern thicker than the first conductive pattern. The first and second conductive patterns are located in the same layer. The first conductive pattern is formed by pattern-etching a conductive layer having a uniform thickness by the subtractive method. The second conductive pattern is formed by forming a pattern-forming groove and then filling the inside of the pattern-forming groove with a conductive material simultaneously with forming a via hole. The first conductive pattern is suitable for an LC pattern for a high-frequency circuit requiring small variations in the width and the thickness of the pattern as well as accuracy in the thickness relative to an insulating pattern, and for a normal conductive pattern requiring impedance matching. The second conductive pattern is suitable for an L pattern for a choke coil.

    摘要翻译： 根据本发明的多层基板包括多个层叠绝缘层和形成在各绝缘层之间的导电图案。 导电图案包括具有预定厚度的第一导电图案和比第一导电图案更厚的第二导电图案。 第一和第二导电图案位于同一层中。 通过减法法对具有均匀厚度的导电层进行图案蚀刻来形成第一导电图案。 第二导电图案通过形成图案形成槽，然后在形成通孔的同时用导电材料填充图案形成槽的内部而形成。 第一导电图案适用于要求图案的宽度和厚度的小变化以及相对于绝缘图案的厚度精度的高频电路的LC图案，以及需要阻抗匹配的正常导电图案 。 第二导电图案适用于扼流线圈的L图案。

    Interconnection element for electric circuits
    9.
    发明申请
    Interconnection element for electric circuits 有权
    电路互连元件

    公开(公告)号：US20090188706A1

    公开(公告)日：2009-07-30

    申请号：US12317707

    申请日：2008-12-23

    申请人： Kimitaka Endo

    发明人： Kimitaka Endo

    IPC分类号： H05K1/02 ,  H05K1/11 ,  B32B37/02 ,  B44C1/22

    CPC分类号： H01R43/0256 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13609 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01322 ,  H05K1/185 ,  H05K3/06 ,  H05K3/4007 ,  H05K3/4015 ,  H05K3/4614 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/10674 ,  H05K2203/0384 ,  H05K2203/0542 ,  H01L2224/05599

    摘要： An interconnection element and method for making same is disclosed. The interconnection element may include a plurality of metal conductors, a plurality of solid metal bumps and a low melting point (LMP) metal layer. The solid metal bumps overly and project in a first direction away from respective ones of the conductors. Each bump has at least one edge bounding the bump in at least a second direction transverse to the first direction. The low melting point (LMP) metal layer has a first face joined to the respective ones of the conductors and bounded in the second direction by at least one edge and a second face joined to the bumps. The edges of the bumps and the LMP layer are aligned in the first direction, and the LMP metal layer has a melting temperature substantially lower than the conductors.

    摘要翻译： 公开了互连元件及其制造方法。 互连元件可以包括多个金属导体，多个固体金属凸块和低熔点（LMP）金属层。 固体金属凸起并且远离相应导体的第一方向突出。 每个凸块具有至少一个沿至少一个横向于第一方向的第二方向限定凸块的边缘。 低熔点（LMP）金属层具有连接到各个导体的第一面，并且通过至少一个边缘和与凸块相连的第二面沿第二方向限定。 凸块和LMP层的边缘在第一方向上对齐，并且LMP金属层的熔化温度基本上低于导体。

    Method of manufacturing the substrate for packaging integrated circuits without multiple photolithography/etching steps
    10.
    发明授权
    Method of manufacturing the substrate for packaging integrated circuits without multiple photolithography/etching steps 有权
    制造没有多次光刻/蚀刻步骤的用于封装集成电路的基板的方法

    公开(公告)号：US07504282B2

    公开(公告)日：2009-03-17

    申请号：US11564003

    申请日：2006-11-28

    申请人： Chi-Chao Tseng

    发明人： Chi-Chao Tseng

    IPC分类号： H01L21/00

    CPC分类号： H05K3/243 ,  H01L21/4846 ,  H01L2924/0002 ,  H05K3/28 ,  H05K3/427 ,  H05K2201/0352 ,  H05K2203/0542 ,  H01L2924/00

    摘要： A method of manufacturing a substrate for packaging ICs is disclosed, which coats a thin conductive layer on the bottom surface of the laminated circuit board, for electrically connecting the pad and the circuit pattern formed on the bottom surface after one line photolithography/etching step. The pad formed on the top surface of the laminated circuit board can be electrically connected to the power applied in the electroplating process through the electroplating layer in the through hole and the conductive layer. Hence, the times of line photolithography/etching steps required for the prior process can be reduced, thereby solving the issues of lowering yield caused by the line photolithography/etching steps.

    摘要翻译： 公开了一种制造用于封装IC的衬底的方法，其在层压电路板的底表面上涂覆薄导电层，用于在一行光刻/蚀刻步骤之后电连接焊盘和形成在底表面上的电路图案。 形成在层压电路板的顶表面上的焊盘可以通过通孔和导电层中的电镀层电连接到在电镀工艺中施加的功率。 因此，可以减少现有技术所需的线光刻/蚀刻步骤的时间，从而解决由线光刻/蚀刻步骤引起的降低产量的问题。