公开(公告)号：US4240845A

公开(公告)日：1980-12-23

申请号：US118257

申请日：1980-02-04

申请人： Ronald P. Esch ,  Robert M. Folsom ,  Cheng-Yih Liu ,  Vincent L. Rideout ,  Donald A. Soderman ,  George T. Wenning

发明人： Ronald P. Esch ,  Robert M. Folsom ,  Cheng-Yih Liu ,  Vincent L. Rideout ,  Donald A. Soderman ,  George T. Wenning

IPC分类号： G11C11/404 ,  H01L21/033 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/26 ,  H01L21/223

CPC分类号： H01L27/1085 ,  G11C11/404 ,  H01L21/033 ,  H01L27/10805

摘要： A dynamic random access memory is fabricated on a monolithic chip of semiconductor material. The memory is formed of an array of memory cells controlled for reading and writing by word and bit lines which are selectively connected to the cells. Each cell is a single field effect transistor structure having improved electrical charge storage capability. The improved charge storage capability of each cell is provided by an electrical capacitance structure uniquely arranged and formed as an integral portion of the field effect transistor structure. The gate electrode of each field effect transistor structure is connected to a predetermined one of said word lines. The drain of each field effect transistor is connected to a predetermined one of said bit lines. The source of each field effect transistor structure is integrally connected to and forms a portion of the uniquely arranged electrical capacitance structure of the field effect transistor structure. The electrical capacitance or storage node structure of each cell has increased electrical charge storage capacity and may be considered as a single capacitor. The single (storage) capacitor of each cell is provided between the source of the field effect transistor, a source of reference potential (reference plane) and the monolithic semiconductor substrate on which the memory is fabricated.The arrangement of the memory cells, the structure and material of each of the memory cells, and a method of fabricating the entire memory is disclosed. Also disclosed is an improved field effect transistor structure and process for fabricating same. The process of fabrication, cell arrangement and the improved storage node of each memory cell, as structurally fabricated and uniquely arranged, provides a monolithic memory having improved density and operating characteristics.

摘要翻译： 在半导体材料的单片芯片上制造动态随机存取存储器。 存储器由被选择性地连接到单元的字和位线读取和写入的存储器单元的阵列形成。 每个单元是具有改进的电荷存储能力的单场效应晶体管结构。 每个单元的改进的电荷存储能力由唯一地排列和形成为场效应晶体管结构的整体部分的电容结构提供。 每个场效应晶体管结构的栅电极连接到预定的一条字线。 每个场效应晶体管的漏极连接到预定的一个位线。 每个场效应晶体管结构的源极整体连接并形成场效应晶体管结构的唯一排列的电容结构的一部分。 每个单元的电容或存储节点结构具有增加的电荷存储容量，并且可以被认为是单个电容器。 每个单元的单个（存储）电容器设置在场效应晶体管的源极，参考电位源（参考平面）和其上制造存储器的单片半导体衬底之间。 存储单元的布置，每个存储单元的结构和材料以及制造整个存储器的方法都被公开。 还公开了一种改进的场效应晶体管结构及其制造方法。 每个存储单元的制造，单元布置和改进的存储节点的过程在结构上制造和独特地布置，提供了具有改进的密度和操作特性的单片存储器。

公开(公告)号：US06251562B1

公开(公告)日：2001-06-26

申请号：US09219586

申请日：1998-12-23

申请人： Gregory Breyta ,  Thomas Carl Clarke ,  Daniel Joseph Dawson ,  Ronald P. Esch ,  Alfred Floyd Renaldo

发明人： Gregory Breyta ,  Thomas Carl Clarke ,  Daniel Joseph Dawson ,  Ronald P. Esch ,  Alfred Floyd Renaldo

IPC分类号： G03C1825

CPC分类号： C08F212/14 ,  G03F7/091 ,  Y10S430/11

摘要： An antireflective composition includes a polyphenolic polymer which has a first repeating unit and a second repeating unit of the formula: wherein each of R1, R2, R3, R4, and R5 is individually a hydroxy group, hydrogen or an azo dye and only one of R1, R2, R3, R4, and R5 is a hydroxy group.

摘要翻译： 抗反射组合物包括具有下式的第一重复单元和第二重复单元的多酚聚合物：其中R 1，R 2，R 3，R 4和R 5各自独立地为羟基，氢或偶氮染料，并且仅一个 R1，R2，R3，R4和R5是羟基。

公开(公告)号：US4219834A

公开(公告)日：1980-08-26

申请号：US850762

申请日：1977-11-11

申请人： Ronald P. Esch ,  Robert M. Folsom ,  Cheng-Yih Liu ,  Vincent L. Rideout ,  Donald A. Soderman ,  G. Thomas Wenning

发明人： Ronald P. Esch ,  Robert M. Folsom ,  Cheng-Yih Liu ,  Vincent L. Rideout ,  Donald A. Soderman ,  G. Thomas Wenning

IPC分类号： G11C11/401 ,  G11C5/06 ,  G11C11/404 ,  G11C11/4097 ,  H01L21/033 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L27/02

CPC分类号： H01L27/1085 ,  G11C11/404 ,  G11C11/4097 ,  G11C5/063 ,  H01L21/033 ,  H01L27/10805

摘要： A dynamic random access memory is fabricated on a monolithic chip of semiconductor material. The memory is formed of an array of memory cells controlled for reading and writing by word and bit lines which are selectively connected to the cells. Each cell is a single field effect transistor structure having improved electrical charge storage capability. The improved charge storage capability of each cell is provided by an electrical capacitance structure uniquely arranged and formed as an integral portion of the field effect transistor structure. The gate electrode of each field effect transistor structure is connected to a predetermined one of said word lines. The drain of each field effect transistor is connected to a predetermined one of said bit lines. The source of each field effect transistor structure is integrally connected to and forms a portion of the uniquely arranged electrical capacitance structure of the field effect transistor structure. The electrical capacitance or storage node structure of each cell has increased electrical charge storage capacity and may be considered as a single capacitor. The single (storage) capacitor of each cell is provided between the source of the field effect transistor, a source of reference potential (reference plane) and the monolithic semiconductor substrate on which the memory is fabricated.The arrangement of the memory cells, the structure and material of each of the memory cells, and a method of fabricating the entire memory is disclosed. Also disclosed is an improved field effect transistor structure and process for fabricating same. The process of fabrication, cell arrangement and the improved storage node of each memory cell, as structurally fabricated and uniquely arranged, provides a monolithic memory having improved density and operating characteristics.

摘要翻译： 在半导体材料的单片芯片上制造动态随机存取存储器。 存储器由被选择性地连接到单元的字和位线读取和写入的存储器单元的阵列形成。 每个单元是具有改进的电荷存储能力的单场效应晶体管结构。 每个单元的改进的电荷存储能力由唯一地排列和形成为场效应晶体管结构的整体部分的电容结构提供。 每个场效应晶体管结构的栅电极连接到预定的一条字线。 每个场效应晶体管的漏极连接到预定的一个位线。 每个场效应晶体管结构的源极整体连接并形成场效应晶体管结构的唯一排列的电容结构的一部分。 每个单元的电容或存储节点结构具有增加的电荷存储容量，并且可以被认为是单个电容器。 每个单元的单个（存储）电容器设置在场效应晶体管的源极，参考电位源（参考平面）和其上制造存储器的单片半导体衬底之间。 存储单元的布置，每个存储单元的结构和材料以及制造整个存储器的方法都被公开。 还公开了一种改进的场效应晶体管结构及其制造方法。 每个存储单元的制造，单元布置和改进的存储节点的过程在结构上制造和独特地布置，提供了具有改进的密度和操作特性的单片存储器。

公开(公告)号：US4186408A

公开(公告)日：1980-01-29

申请号：US819641

申请日：1977-07-27

申请人： Ronald P. Esch ,  Patrick C. Huang

发明人： Ronald P. Esch ,  Patrick C. Huang

IPC分类号： H01L21/316 ,  H01L21/32 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/32

摘要： The invention is a process of fabricating semiconductor devices including an insulating film across the surface that has a planar configuration. Alternatively, the film may be of uniform thickness and non-planar configuration. Both the planar and uniform thickness characteristics of the insulating film permit openings to be formed therein without over etching a defined surface area and conductors to be formed thereon without broadening. An important feature of the invention is utilizing the differential growth rate of films on semiconductor surfaces and/or selection of a suitable initial film thickness as a diffusion mask. The initial film thickness also contributes to a planar or uniform film thickness or other configuration across the device.

摘要翻译： 本发明是制造半导体器件的方法，该半导体器件包括跨过表面的绝缘膜，该绝缘膜具有平面构型。 或者，膜可以具有均匀的厚度和非平面构造。 绝缘膜的平面和均匀厚度特性都允许在其中形成开口，而不会过度蚀刻限定的表面积，并且在其上形成的导体不会变宽。 本发明的一个重要特征是利用半导体表面上的膜的差分生长速率和/或适当的初始膜厚度的选择作为扩散掩模。 初始膜厚度还有助于平面或均匀的膜厚度或跨装置的其它构型。