公开(公告)号：US20110093735A1

公开(公告)日：2011-04-21

申请号：US12923801

申请日：2010-10-07

申请人： Hideyuki Yoko ,  Naohisa Nishioka ,  Chikara Kondo ,  Ryuji Takishita

发明人： Hideyuki Yoko ,  Naohisa Nishioka ,  Chikara Kondo ,  Ryuji Takishita

IPC分类号： G06F1/08

CPC分类号： G11C7/222 ,  G06F1/10 ,  G11C5/02 ,  G11C29/02 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  H01L2224/16145 ,  H01L2924/01037 ,  H01L2924/01055 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/15311 ,  H01L2924/00

摘要： Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that equalizes the periods of time required between the reception of the read command and the outputting of the read data from the data output circuit among the core chips. With this arrangement, a sufficient latch margin for read data to be input can be secured on the interface chip side. Furthermore, as the output timing is adjusted on each core chip side, there is no need to prepare the same number of latch timing control circuits as the number of core chips on the interface chip side.

摘要翻译： 每个核心芯片包括数据输出电路，其响应于读取命令将读取数据输出到接口芯片;以及输出定时调整电路，其将接收到读取命令和输出读取命令之间所需的时间相等 从核心芯片中的数据输出电路读取数据。 通过这种布置，可以在接口芯片侧确保用于要输入的读取数据的足够的锁存余量。 此外，由于在每个芯片侧调整输出定时，因此不需要准备与接口芯片侧的芯片数相同数量的锁存定时控制电路。

公开(公告)号：US08599641B2

公开(公告)日：2013-12-03

申请号：US12923801

申请日：2010-10-07

申请人： Hideyuki Yoko ,  Naohisa Nishioka ,  Chikara Kondo ,  Ryuji Takishita

发明人： Hideyuki Yoko ,  Naohisa Nishioka ,  Chikara Kondo ,  Ryuji Takishita

IPC分类号： G11C8/00

CPC分类号： G11C7/222 ,  G06F1/10 ,  G11C5/02 ,  G11C29/02 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  H01L2224/16145 ,  H01L2924/01037 ,  H01L2924/01055 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/15311 ,  H01L2924/00

摘要： Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that equalizes the periods of time required between the reception of the read command and the outputting of the read data from the data output circuit among the core chips. With this arrangement, a sufficient latch margin for read data to be input can be secured on the interface chip side. Furthermore, as the output timing is adjusted on each core chip side, there is no need to prepare the same number of latch timing control circuits as the number of core chips on the interface chip side.

摘要翻译： 每个核心芯片包括数据输出电路，其响应于读取命令将读取数据输出到接口芯片;以及输出定时调整电路，其将接收到读取命令和输出读取命令之间所需的时间相等 从核心芯片中的数据输出电路读取数据。 通过这种布置，可以在接口芯片侧确保用于要输入的读取数据的足够的锁存余量。 此外，由于在每个芯片侧调整输出定时，因此不需要准备与接口芯片侧的芯片数相同数量的锁存定时控制电路。

公开(公告)号：US08803545B2

公开(公告)日：2014-08-12

申请号：US12929330

申请日：2011-01-14

申请人： Hideyuki Yoko ,  Kentaro Hara ,  Ryuji Takishita

发明人： Hideyuki Yoko ,  Kentaro Hara ,  Ryuji Takishita

IPC分类号： G01R31/26

CPC分类号： G06F1/12 ,  G11C5/04 ,  G11C29/02 ,  G11C29/025 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06596 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： To provide a semiconductor device including an interface chip and a core chip and a measurement-target signal line and a reference signal line each including a through silicon via provided in the core chip and electrically connecting the interface chip and the core chip. The interface chip outputs a test clock generated by a first signal generation circuit to the core chip. The core chip includes a second signal generation circuit that generates a predetermined measurement signal from the test clock, and outputs the predetermined measurement signal to the measurement-target signal line and the reference signal line in a simultaneous manner. Further, the interface chip detects a phase difference of a plurality of predetermined measurement signals input via the measurement-target signal line and the reference signal line by an operational amplifier, and outputs a test result to a determination circuit.

摘要翻译： 为了提供一种包括接口芯片和芯片的半导体器件，以及测量目标信号线和参考信号线，每个包括设置在芯片芯片中的穿硅通孔，并且电连接接口芯片和芯片芯片。 接口芯片将由第一信号发生电路产生的测试时钟输出到核心芯片。 核心芯片包括从测试时钟产生预定测量信号的第二信号产生电路，并以预定的测量信号同时输出到测量目标信号线和参考信号线。 此外，接口芯片通过运算放大器检测经由测量对象信号线和参考信号线输入的多个预定测量信号的相位差，并将测试结果输出到确定电路。

公开(公告)号：US20110175639A1

公开(公告)日：2011-07-21

申请号：US12929330

申请日：2011-01-14

申请人： Hideyuki Yoko ,  Kentaro Hara ,  Ryuji Takishita

发明人： Hideyuki Yoko ,  Kentaro Hara ,  Ryuji Takishita

IPC分类号： G01R31/26 ,  H01L23/48

CPC分类号： G06F1/12 ,  G11C5/04 ,  G11C29/02 ,  G11C29/025 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06596 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： To provide a semiconductor device including an interface chip and a core chip and a measurement-target signal line and a reference signal line each including a through silicon via provided in the core chip and electrically connecting the interface chip and the core chip. The interface chip outputs a test clock generated by a first signal generation circuit to the core chip. The core chip includes a second signal generation circuit that generates a predetermined measurement signal from the test clock, and outputs the predetermined measurement signal to the measurement-target signal line and the reference signal line in a simultaneous manner. Further, the interface chip detects a phase difference of a plurality of predetermined measurement signals input via the measurement-target signal line and the reference signal line by an operational amplifier, and outputs a test result to a determination circuit.

摘要翻译： 为了提供一种包括接口芯片和芯片的半导体器件，以及测量目标信号线和参考信号线，每个包括设置在芯片芯片中的穿硅通孔，并且电连接接口芯片和芯片芯片。 接口芯片将由第一信号发生电路产生的测试时钟输出到核心芯片。 核心芯片包括从测试时钟产生预定测量信号的第二信号产生电路，并以预定的测量信号同时输出到测量目标信号线和参考信号线。 此外，接口芯片通过运算放大器检测经由测量对象信号线和参考信号线输入的多个预定测量信号的相位差，并将测试结果输出到确定电路。

公开(公告)号：US08400805B2

公开(公告)日：2013-03-19

申请号：US12929668

申请日：2011-02-07

申请人： Hideyuki Yoko

发明人： Hideyuki Yoko

IPC分类号： G11C5/00 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C11/4093 ,  G11C5/04 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/4082 ,  G11C29/702 ,  H01L2224/16145

摘要： A semiconductor device according to the present invention includes plural controlled chips CC0 to CC7 that hold mutually different layer information, and a control chip IF that supplies in common layer address signals A13 to A15 and a command signal ICMD to the controlled chips. Each bit that constitutes the layer address signals A13 to A15 is transmitted via at least two through silicon vias that are connected in parallel for each controlled chip out of plural first through silicon vias. Each bit that constitutes the command signal ICMD is transmitted via one corresponding through silicon via that is selected by an output switching circuit and an input switching circuit. With this configuration, the layer address signals A13 to A15 reach the controlled chips earlier than the command signal ICMD.

摘要翻译： 根据本发明的半导体器件包括保持相互不同的层信息的多个受控芯片CC0至CC7，以及将共同层地址信号A13至A15和命令信号ICMD提供给受控芯片的控制芯片IF。 构成层地址信号A13至A15的每个位通过至少两个穿过硅通孔的硅通孔传输，每个通孔通过硅通孔从多个第一通孔中的每个受控芯片并联连接。 构成命令信号ICMD的每一位通过由输出开关电路和输入开关电路选择的硅通过一个相应的传输。 利用这种配置，层地址信号A13至A15比命令信号ICMD早到达受控芯片。

公开(公告)号：US08274847B2

公开(公告)日：2012-09-25

申请号：US12964304

申请日：2010-12-09

申请人： Hideyuki Yoko

发明人： Hideyuki Yoko

IPC分类号： G11C16/04

CPC分类号： G11C5/14 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4074 ,  H01L25/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15311 ,  H05K1/18 ,  H01L2924/00

摘要： To provide a semiconductor system including a plurality of core chips and an interface chip that controls the core chips. Each of the core chips includes an internal voltage generating circuit. The interface chip includes an unused chip information holding circuit that stores therein unused chip information of the core chips. The core chips respectively receive the unused chip information from the unused chip information holding circuit. When the unused chip information indicates an unused state, the internal voltage generating circuits are inactivated, and when the unused chip information indicates a used state, the internal voltage generating circuits are activated. With this configuration, unnecessary power consumption by the unused chips is reduced.

摘要翻译： 提供包括多个核心芯片的半导体系统和控制核心芯片的接口芯片。 每个核心芯片包括内部电压产生电路。 接口芯片包括未使用的芯片信息保持电路，其存储芯芯的未使用的芯片信息。 核心芯片分别从未使用的芯片信息保持电路接收未使用的芯片信息。 当未使用的芯片信息表示未使用状态时，内部电压产生电路被去激活，并且当未使用的芯片信息指示使用状态时，内部电压产生电路被激活。 利用这种配置，可以减少未使用芯片的不必要的功耗。

公开(公告)号：US20110084729A1

公开(公告)日：2011-04-14

申请号：US12923752

申请日：2010-10-06

申请人： Hideyuki Yoko

发明人： Hideyuki Yoko

IPC分类号： H03K19/00 ,  H03K17/00

CPC分类号： H03K19/018521 ,  G11C5/02 ,  G11C5/063 ,  H01L2224/16145 ,  H01L2924/01037 ,  H01L2924/01055 ,  H01L2924/15311 ,  H04L25/028 ,  H04L25/0292

摘要： One interface chip and a plurality of core chips are electrically connected via a plurality of through silicon vias. A data signal of a driver circuit is input into the core chip via any one of the through silicon vias. An output switching circuit activates any one of tri-state inverters and selects one of the through silicon vias. The tri-state inverters amplify the data signal and transmit it to the through silicon via. Similarly, an input switching circuit activates any one of tri-state inverters. These tri-state inverters also amplify the data signal transmitted from the through silicon via and supply it to the receiver circuit.

摘要翻译： 一个接口芯片和多个芯片芯片通过多个通孔硅电气电连接。 驱动电路的数据信号通过硅通孔中的任何一个而被输入到芯片芯片中。 输出开关电路激活三态反相器中的任何一个，并选择贯穿硅通孔之一。 三态反相器放大数据信号并将其传送到硅通孔。 类似地，输入开关电路激活三态逆变器中的任何一个。 这些三态反相器还放大从硅通孔传输的数据信号并将其提供给接收器电路。

公开(公告)号：US07595645B2

公开(公告)日：2009-09-29

申请号：US11580902

申请日：2006-10-16

申请人： Hiroki Fujisawa ,  Hideyuki Yoko

发明人： Hiroki Fujisawa ,  Hideyuki Yoko

IPC分类号： G01R35/00 ,  H03K19/094

CPC分类号： H04L25/0278 ,  H04L25/12

摘要： Impedance adjusting transistors are once inactivated on every occasion of changing an impedance adjusting code. After restoring the potential to an initially set potential by once inactivating the impedance adjusting transistors, the state of the transistors is switched according to the impedance adjusting code. By starting the potential from the initially set potential at the time of switching the state of the transistors, no switching noise is generated. Since no switching noise is generated, a comparator always carries out stable comparison and judgment and thus there is obtained a calibration circuit that ensures stable outputs.

摘要翻译： 在改变阻抗调整码的每个场合，阻抗调整晶体管一旦失效。 通过一旦使阻抗调节晶体管钝化，将电位恢复到初始设定电位后，根据阻抗调整代码切换晶体管的状态。 通过在切换晶体管的状态时从初始设定电位开始电位，不产生开关噪声。 由于不产生开关噪声，所以比较器总是执行稳定的比较和判断，从而获得确保稳定输出的校准电路。

公开(公告)号：US20120320654A1

公开(公告)日：2012-12-20

申请号：US13595824

申请日：2012-08-27

申请人： Hideyuki Yoko

发明人： Hideyuki Yoko

IPC分类号： G11C5/06

CPC分类号： G11C5/14 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4074 ,  H01L25/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15311 ,  H05K1/18 ,  H01L2924/00

摘要： A system that includes a first semiconductor chip, a second semiconductor chip, and a controller chip. The first semiconductor chip includes a first terminal, a second terminal, a first circuit electrically coupled to the second terminal, a second circuit electrically coupled to the first terminal and the first circuit, and a third circuit electrically coupled to the second circuit. The second semiconductor chip includes a third terminal, a fourth terminal, a fourth circuit electrically coupled to the fourth terminal, a fifth circuit electrically coupled to the third terminal and the fourth circuit, and a sixth circuit electrically coupled to the fifth circuit.

摘要翻译： 一种包括第一半导体芯片，第二半导体芯片和控制器芯片的系统。 第一半导体芯片包括第一端子，第二端子，电耦合到第二端子的第一电路，电耦合到第一端子和第一电路的第二电路，以及电耦合到第二电路的第三电路。 第二半导体芯片包括第三端子，第四端子，电耦合到第四端子的第四电路，电耦合到第三端子和第四电路的第五电路，以及电耦合到第五电路的第六电路。

公开(公告)号：US20120195136A1

公开(公告)日：2012-08-02

申请号：US12929668

申请日：2011-02-07

申请人： Hideyuki Yoko

发明人： Hideyuki Yoko

IPC分类号： G11C8/18 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C11/4093 ,  G11C5/04 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/4082 ,  G11C29/702 ,  H01L2224/16145

摘要： A semiconductor device according to the present invention includes plural controlled chips CC0 to CC7 that hold mutually different layer information, and a control chip IF that supplies in common layer address signals A13 to A15 and a command signal ICMD to the controlled chips. Each bit that constitutes the layer address signals A13 to A15 is transmitted via at least two through silicon vias that are connected in parallel for each controlled chip out of plural first through silicon vias. Each bit that constitutes the command signal ICMD is transmitted via one corresponding through silicon via that is selected by an output switching circuit and an input switching circuit. With this configuration, the layer address signals A13 to A15 reach the controlled chips earlier than the command signal ICMD.

摘要翻译： 根据本发明的半导体器件包括保持相互不同的层信息的多个受控芯片CC0至CC7，以及将共同层地址信号A13至A15和命令信号ICMD提供给受控芯片的控制芯片IF。 构成层地址信号A13至A15的每个位通过至少两个穿过硅通孔的硅通孔传输，每个通孔通过硅通孔从多个第一通孔中的每个受控芯片并联连接。 构成命令信号ICMD的每一位通过由输出开关电路和输入开关电路选择的硅通过一个相应的传输。 利用这种配置，层地址信号A13至A15比命令信号ICMD早到达受控芯片。