公开(公告)号：US20110057819A1

公开(公告)日：2011-03-10

申请号：US12923826

申请日：2010-10-08

申请人： Akira Ide ,  Ryuji Takishita

发明人： Akira Ide ,  Ryuji Takishita

IPC分类号： H03M9/00 ,  H01L23/48 ,  H01L25/00

CPC分类号： H01L25/0657 ,  G11C5/02 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05096 ,  H01L2224/05567 ,  H01L2224/16145 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01037 ,  H01L2924/01055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2224/05552 ,  H01L2924/00

摘要： In a stacked semiconductor device in which a plurality of through silicon vias used for data transfer are shared among a plurality of semiconductor chips, a first semiconductor chip included in the semiconductor chips holds through silicon via switching information for specifying a through silicon via among the through silicon vias to be used for data transfer, and transfers the through silicon via switching information to a second semiconductor chip included in the semiconductor chips. According to the present invention, because the through silicon via switching information is transferred from the first semiconductor chip to the second semiconductor chip, a circuit for storing the through silicon via switching information in a nonvolatile manner is not required in the second semiconductor chip. With this arrangement, a chip area of the second semiconductor chip can be reduced.

摘要翻译： 在其中在多个半导体芯片之间共享用于数据传输的多个通孔的堆叠半导体器件中，包括在半导体芯片中的第一半导体芯片通过硅经由用于指定贯穿硅通孔的开关信息 用于数据传输的硅通孔，并且通过切换信息将通过硅传送到包括在半导体芯片中的第二半导体芯片。 根据本发明，由于通过硅通孔切换信息从第一半导体芯片传送到第二半导体芯片，所以在第二半导体芯片中不需要用于以非易失性方式通过切换信息存储贯穿硅的电路。 利用这种布置，可以减少第二半导体芯片的芯片面积。

公开(公告)号：US08310382B2

公开(公告)日：2012-11-13

申请号：US12923826

申请日：2010-10-08

申请人： Akira Ide ,  Ryuji Takishita

发明人： Akira Ide ,  Ryuji Takishita

IPC分类号： H03M9/00

CPC分类号： H01L25/0657 ,  G11C5/02 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05096 ,  H01L2224/05567 ,  H01L2224/16145 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01037 ,  H01L2924/01055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2224/05552 ,  H01L2924/00

摘要： In a stacked semiconductor device in which a plurality of through silicon vias used for data transfer are shared among a plurality of semiconductor chips, a first semiconductor chip included in the semiconductor chips holds through silicon via switching information for specifying a through silicon via among the through silicon vias to be used for data transfer, and transfers the through silicon via switching information to a second semiconductor chip included in the semiconductor chips. According to the present invention, because the through silicon via switching information is transferred from the first semiconductor chip to the second semiconductor chip, a circuit for storing the through silicon via switching information in a nonvolatile manner is not required in the second semiconductor chip. With this arrangement, a chip area of the second semiconductor chip can be reduced.

摘要翻译： 在其中在多个半导体芯片之间共享用于数据传输的多个通孔的堆叠半导体器件中，包括在半导体芯片中的第一半导体芯片通过硅经由用于指定贯穿硅通孔的开关信息 用于数据传输的硅通孔，并且通过切换信息将通过硅传送到包括在半导体芯片中的第二半导体芯片。 根据本发明，由于通过硅通孔切换信息从第一半导体芯片传送到第二半导体芯片，所以在第二半导体芯片中不需要用于以非易失性方式通过切换信息存储贯穿硅的电路。 利用这种布置，可以减少第二半导体芯片的芯片面积。

公开(公告)号：US20110093735A1

公开(公告)日：2011-04-21

申请号：US12923801

申请日：2010-10-07

申请人： Hideyuki Yoko ,  Naohisa Nishioka ,  Chikara Kondo ,  Ryuji Takishita

发明人： Hideyuki Yoko ,  Naohisa Nishioka ,  Chikara Kondo ,  Ryuji Takishita

IPC分类号： G06F1/08

CPC分类号： G11C7/222 ,  G06F1/10 ,  G11C5/02 ,  G11C29/02 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  H01L2224/16145 ,  H01L2924/01037 ,  H01L2924/01055 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/15311 ,  H01L2924/00

摘要： Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that equalizes the periods of time required between the reception of the read command and the outputting of the read data from the data output circuit among the core chips. With this arrangement, a sufficient latch margin for read data to be input can be secured on the interface chip side. Furthermore, as the output timing is adjusted on each core chip side, there is no need to prepare the same number of latch timing control circuits as the number of core chips on the interface chip side.

摘要翻译： 每个核心芯片包括数据输出电路，其响应于读取命令将读取数据输出到接口芯片;以及输出定时调整电路，其将接收到读取命令和输出读取命令之间所需的时间相等 从核心芯片中的数据输出电路读取数据。 通过这种布置，可以在接口芯片侧确保用于要输入的读取数据的足够的锁存余量。 此外，由于在每个芯片侧调整输出定时，因此不需要准备与接口芯片侧的芯片数相同数量的锁存定时控制电路。

公开(公告)号：US08803545B2

公开(公告)日：2014-08-12

申请号：US12929330

申请日：2011-01-14

申请人： Hideyuki Yoko ,  Kentaro Hara ,  Ryuji Takishita

发明人： Hideyuki Yoko ,  Kentaro Hara ,  Ryuji Takishita

IPC分类号： G01R31/26

CPC分类号： G06F1/12 ,  G11C5/04 ,  G11C29/02 ,  G11C29/025 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06596 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： To provide a semiconductor device including an interface chip and a core chip and a measurement-target signal line and a reference signal line each including a through silicon via provided in the core chip and electrically connecting the interface chip and the core chip. The interface chip outputs a test clock generated by a first signal generation circuit to the core chip. The core chip includes a second signal generation circuit that generates a predetermined measurement signal from the test clock, and outputs the predetermined measurement signal to the measurement-target signal line and the reference signal line in a simultaneous manner. Further, the interface chip detects a phase difference of a plurality of predetermined measurement signals input via the measurement-target signal line and the reference signal line by an operational amplifier, and outputs a test result to a determination circuit.

摘要翻译： 为了提供一种包括接口芯片和芯片的半导体器件，以及测量目标信号线和参考信号线，每个包括设置在芯片芯片中的穿硅通孔，并且电连接接口芯片和芯片芯片。 接口芯片将由第一信号发生电路产生的测试时钟输出到核心芯片。 核心芯片包括从测试时钟产生预定测量信号的第二信号产生电路，并以预定的测量信号同时输出到测量目标信号线和参考信号线。 此外，接口芯片通过运算放大器检测经由测量对象信号线和参考信号线输入的多个预定测量信号的相位差，并将测试结果输出到确定电路。

公开(公告)号：US08604835B2

公开(公告)日：2013-12-10

申请号：US12871564

申请日：2010-08-30

申请人： Koji Kuroki ,  Ryuji Takishita

发明人： Koji Kuroki ,  Ryuji Takishita

IPC分类号： G01R25/00 ,  H03D13/00

CPC分类号： H03L7/085 ,  G11C7/222 ,  H03K5/249 ,  H03L7/0814 ,  H03L7/0816

摘要： In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. Also provided an equalizing circuit precharging/equalizing the two sense nodes (FIG. 2).

摘要翻译： 在半导体器件中，在GND和两个感测节点之间提供第一至第三对nMOS晶体管，并且在两个感测节点和电源之间提供第一至第三对pMOS晶体管对。 第一内部时钟信号及其反相信号分别被提供给第一对nMOS晶体管和第二对nMOS晶体管的栅极。 互补的外部时钟信号被提供给第三对nMOS晶体管和第三对pMOS晶体管的栅极。 第二内部时钟信号的反相形式和第二内部时钟信号被提供给第一和第二对pMOS晶体管的栅极。 两个感测节点连接到差分放大器的输入。 差分放大器的输出由锁存电路锁存。 还提供了均衡电路对两个感测节点进行预充电/均衡（图2）。

公开(公告)号：US08599641B2

公开(公告)日：2013-12-03

申请号：US12923801

申请日：2010-10-07

申请人： Hideyuki Yoko ,  Naohisa Nishioka ,  Chikara Kondo ,  Ryuji Takishita

发明人： Hideyuki Yoko ,  Naohisa Nishioka ,  Chikara Kondo ,  Ryuji Takishita

IPC分类号： G11C8/00

CPC分类号： G11C7/222 ,  G06F1/10 ,  G11C5/02 ,  G11C29/02 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  H01L2224/16145 ,  H01L2924/01037 ,  H01L2924/01055 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/15311 ,  H01L2924/00

摘要： Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that equalizes the periods of time required between the reception of the read command and the outputting of the read data from the data output circuit among the core chips. With this arrangement, a sufficient latch margin for read data to be input can be secured on the interface chip side. Furthermore, as the output timing is adjusted on each core chip side, there is no need to prepare the same number of latch timing control circuits as the number of core chips on the interface chip side.

摘要翻译： 每个核心芯片包括数据输出电路，其响应于读取命令将读取数据输出到接口芯片;以及输出定时调整电路，其将接收到读取命令和输出读取命令之间所需的时间相等 从核心芯片中的数据输出电路读取数据。 通过这种布置，可以在接口芯片侧确保用于要输入的读取数据的足够的锁存余量。 此外，由于在每个芯片侧调整输出定时，因此不需要准备与接口芯片侧的芯片数相同数量的锁存定时控制电路。

公开(公告)号：US20110175639A1

公开(公告)日：2011-07-21

申请号：US12929330

申请日：2011-01-14

申请人： Hideyuki Yoko ,  Kentaro Hara ,  Ryuji Takishita

发明人： Hideyuki Yoko ,  Kentaro Hara ,  Ryuji Takishita

IPC分类号： G01R31/26 ,  H01L23/48

CPC分类号： G06F1/12 ,  G11C5/04 ,  G11C29/02 ,  G11C29/025 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06596 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： To provide a semiconductor device including an interface chip and a core chip and a measurement-target signal line and a reference signal line each including a through silicon via provided in the core chip and electrically connecting the interface chip and the core chip. The interface chip outputs a test clock generated by a first signal generation circuit to the core chip. The core chip includes a second signal generation circuit that generates a predetermined measurement signal from the test clock, and outputs the predetermined measurement signal to the measurement-target signal line and the reference signal line in a simultaneous manner. Further, the interface chip detects a phase difference of a plurality of predetermined measurement signals input via the measurement-target signal line and the reference signal line by an operational amplifier, and outputs a test result to a determination circuit.

摘要翻译： 为了提供一种包括接口芯片和芯片的半导体器件，以及测量目标信号线和参考信号线，每个包括设置在芯片芯片中的穿硅通孔，并且电连接接口芯片和芯片芯片。 接口芯片将由第一信号发生电路产生的测试时钟输出到核心芯片。 核心芯片包括从测试时钟产生预定测量信号的第二信号产生电路，并以预定的测量信号同时输出到测量目标信号线和参考信号线。 此外，接口芯片通过运算放大器检测经由测量对象信号线和参考信号线输入的多个预定测量信号的相位差，并将测试结果输出到确定电路。

公开(公告)号：US20110050304A1

公开(公告)日：2011-03-03

申请号：US12871564

申请日：2010-08-30

申请人： Koji Kuroki ,  Ryuji Takishita

发明人： Koji Kuroki ,  Ryuji Takishita

IPC分类号： H03L7/06

CPC分类号： H03L7/085 ,  G11C7/222 ,  H03K5/249 ,  H03L7/0814 ,  H03L7/0816

摘要： In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. Also provided an equalizing circuit precharging/equalizing the two sense nodes (FIG. 2).

摘要翻译： 在半导体器件中，在GND和两个感测节点之间提供第一至第三对nMOS晶体管，并且在两个感测节点和电源之间提供第一至第三对pMOS晶体管对。 第一内部时钟信号及其反相信号分别被提供给第一对nMOS晶体管和第二对nMOS晶体管的栅极。 互补的外部时钟信号被提供给第三对nMOS晶体管和第三对pMOS晶体管的栅极。 第二内部时钟信号的反相形式和第二内部时钟信号被提供给第一和第二对pMOS晶体管的栅极。 两个感测节点连接到差分放大器的输入。 差分放大器的输出由锁存电路锁存。 还提供了均衡电路对两个感测节点进行预充电/均衡（图2）。

公开(公告)号：US07576579B2

公开(公告)日：2009-08-18

申请号：US11892525

申请日：2007-08-23

申请人： Hiroki Fujisawa ,  Ryuji Takishita

发明人： Hiroki Fujisawa ,  Ryuji Takishita

IPC分类号： H03L7/06

CPC分类号： H03L7/0812

摘要： A DLL circuit includes a first delay adjusting circuit that adjusts an amount of delay of a frequency-divided signal CK1, a second delay adjusting circuit that adjusts an amount of delay of a frequency-divided signal CK2, a synthesizing circuit that synthesizes outputs of these delay adjusting circuits to generate an internal clock signal, and supplies the internal clock signal to a real path, a clock driver that receives the output of the first delay adjusting circuit and supplies the output to a replica path, and a clock driver that receives the output of the second delay adjusting circuit. These clock drivers have substantially the same circuit configuration. Accordingly, even when the power supply voltage fluctuates, influences of the fluctuations on the respective frequency-divided signals are almost equal. Thus, deterioration of the function of the DLL circuit due to fluctuations of the power supply voltage can be prevented.

摘要翻译： DLL电路包括调整分频信号CK1的延迟量的第一延迟调整电路，调整分频信号CK2的延迟量的第二延迟调整电路，合成这些信号的输出的合成电路 延迟调整电路以产生内部时钟信号，并将内部时钟信号提供给实际路径;时钟驱动器，接收第一延迟调整电路的输出并将输出提供给副本路径;以及时钟驱动器，其接收 输出第二延迟调整电路。 这些时钟驱动器具有基本上相同的电路配置。 因此，即使电源电压波动，各分频信号的波动的影响也几乎相等。 因此，可以防止由于电源电压的波动引起的DLL电路的功能的劣化。

公开(公告)号：US07477083B2

公开(公告)日：2009-01-13

申请号：US11585206

申请日：2006-10-24

申请人： Hiroki Fujisawa ,  Ryuji Takishita

发明人： Hiroki Fujisawa ,  Ryuji Takishita

IPC分类号： H03L7/00

CPC分类号： H03K5/131 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

摘要： A delay amount variable circuit (8) adapted to change a delay amount according to a ZQ calibration result is inserted in a path of a DQ replica system. The delay amount of the path of the DQ replica system is variable and is adjusted so as to make constant a timing skew difference between a DQ buffer system and the DQ replica system. The ZQ calibration result changes depending on variations in temperature, voltage, and manufacture. Therefore, by obtaining the delay amount corresponding to these variations, there are obtained a DLL circuit with high accuracy that can make the skew difference constant, and a semiconductor device incorporating such a DLL circuit.

摘要翻译： 适于根据ZQ校准结果改变延迟量的延迟量可变电路（8）被插入到DQ复制系统的路径中。 DQ复制系统的路径的延迟量是可变的并且被调整以使得DQ缓冲器系统和DQ复制系统之间的定时偏差差异恒定。 ZQ校准结果根据温度，电压和制造的变化而变化。 因此，通过获得与这些变化相对应的延迟量，可以获得可以使偏差差异恒定的高精度的DLL电路，以及并入这样的DLL电路的半导体器件。