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39 条记录 (耗时 0.053 秒)

    Non-volatile memory device
    1.
    发明授权
    Non-volatile memory device 有权
    非易失性存储器件

    公开(公告)号：US09000511B2

    公开(公告)日：2015-04-07

    申请号：US13529621

    申请日：2012-06-21

    申请人： Sung-Il Chang ,  Young-Woo Park

    发明人： Sung-Il Chang ,  Young-Woo Park

    IPC分类号： H01L29/792 ,  H01L27/115

    CPC分类号： H01L21/764 ,  H01L21/76224 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/792

    摘要： A non-volatile memory device includes a substrate having an active region defined by a device isolation region that has a trench and an air gap, a device isolation pattern positioned at a lower portion of the trench, a memory cell layer including a tunnel insulation layer, a trap insulation layer and a blocking insulation layer that are sequentially stacked on the active region and one of which extends from the active region toward the device isolation region encloses top of the air gap whose bottom is defined by a layer other than that of the top, and a control gate electrode positioned on the cell structure. The one of the insulation layer extending includes a recess at a region corresponding to the center of the air gap.

    摘要翻译： 非易失性存储器件包括具有由具有沟槽和气隙的器件隔离区限定的有源区的衬底，位于沟槽下部的器件隔离图案，包括隧道绝缘层的存储单元层 ，顺序堆叠在有源区上并且其中一个从有源区向器件隔离区延伸的陷阱绝缘层和阻挡绝缘层包围气隙的顶部，其底部由不同于 顶部和位于电池结构上的控制栅电极。 绝缘层延伸的一个包括在对应于气隙的中心的区域处的凹部。

    Three-dimensional semiconductor devices
    3.
    发明授权
    Three-dimensional semiconductor devices 有权
    三维半导体器件

    公开(公告)号：US08872183B2

    公开(公告)日：2014-10-28

    申请号：US13366057

    申请日：2012-02-03

    申请人： Sung-Il Chang ,  Changhyun Lee ,  Byoungkeun Son ,  Jin-Soo Lim

    发明人： Sung-Il Chang ,  Changhyun Lee ,  Byoungkeun Son ,  Jin-Soo Lim

    IPC分类号： H01L29/04 ,  H01L21/822 ,  H01L27/115 ,  H01L27/06

    CPC分类号： H01L27/11582 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31111 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11556 ,  H01L29/4232 ,  H01L29/42372

    摘要： Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.

    摘要翻译： 提供三维半导体器件。 三维半导体器件包括衬底，衬底上的缓冲层。 缓冲层包括具有相对于衬底的蚀刻选择性的材料。 在与衬底相对的缓冲层上提供包括交替绝缘图案和导电图案的多层堆叠。 一个或多个有源图案分别延伸穿过多层堆叠的交替绝缘图案和导电图案并进入缓冲层。 还讨论了相关的制造方法。

    THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME
    5.
    发明申请
    THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：US20120049268A1

    公开(公告)日：2012-03-01

    申请号：US13222173

    申请日：2011-08-31

    申请人： Sung Il Chang ,  Young Woo Park ,  Jae Goo Lee

    发明人： Sung Il Chang ,  Young Woo Park ,  Jae Goo Lee

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/42324 ,  H01L29/4234

    摘要： A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes.

    摘要翻译： 一种3D半导体器件包括：电极结构，其具有堆叠在基板上的电极，穿透电极结构的半导体图案，插入在半导体图案和电极结构之间的电荷存储图案，以及插入在电荷存储图案和电极结构之间的绝缘图案。 每个隔离绝缘图案包围半导体图案，并且电荷存储图案彼此水平间隔并且以这样的方式配置，以使得每个隔离绝缘图案围绕相应的一个半导体图案设置。 而且，每个电荷存储图案包括多个水平段，每个水平段插入垂直相邻的电极之间。

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权
    三维半导体存储器件

    公开(公告)号：US20120043673A1

    公开(公告)日：2012-02-23

    申请号：US13198234

    申请日：2011-08-04

    申请人： SUNG-IL CHANG ,  Youngwoo Park ,  Kwang Soo Seol

    发明人： SUNG-IL CHANG ,  Youngwoo Park ,  Kwang Soo Seol

    IPC分类号： H01L23/52

    CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    摘要： Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate.

    摘要翻译： 提供三维半导体器件。 一种器件包括：电极结构，包括依次层叠在衬底上的导电图案，穿透电极结构的半导体图案，以及包括与导电图案相邻的沟道区域和沟道区域之间的垂直相邻区域;以及从外侧壁延伸的半导体连接层 的半导体图案以将半导体图案连接到基板。

    NONVOLATILE MEMORY DEVICE AND METHOD OF READING THE SAME
    7.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD OF READING THE SAME 审中-公开
    非易失存储器件及其读取方法

    公开(公告)号：US20110205802A1

    公开(公告)日：2011-08-25

    申请号：US13029947

    申请日：2011-02-17

    申请人： Byeong-In CHOE ,  Sung-Il Chang ,  Changseok Kang

    发明人： Byeong-In CHOE ,  Sung-Il Chang ,  Changseok Kang

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/26

    摘要： Provided are a nonvolatile memory device and a method of reading the same. The nonvolatile memory device includes: a memory cell; a transistor disposed between a common source line and the memory cell; and a control logic for controlling a bias voltage of the transistor to reduce the amount of current flowing into the common source line during a read operation. The method includes: applying a read voltage to the memory cell; and controlling a bias voltage of the transistor to reduce the amount of current flowing into the common source line.

    摘要翻译： 提供一种非易失性存储器件及其读取方法。 非易失性存储器件包括：存储单元; 设置在公共源极线和存储器单元之间的晶体管; 以及用于控制晶体管的偏置电压以减少在读取操作期间流入公共源极线的电流量的控制逻辑。 该方法包括：向存储单元施加读取电压; 以及控制晶体管的偏置电压以减少流入公共源极线的电流量。

    Three dimensional semiconductor memory devices and methods of fabricating the same
    10.
    发明授权
    Three dimensional semiconductor memory devices and methods of fabricating the same 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：US08952443B2

    公开(公告)日：2015-02-10

    申请号：US13222173

    申请日：2011-08-31

    申请人： Sung-Il Chang ,  Young Woo Park ,  Jae Goo Lee

    发明人： Sung-Il Chang ,  Young Woo Park ,  Jae Goo Lee

    IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L21/28

    CPC分类号： H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/42324 ,  H01L29/4234

    摘要： A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes.

    摘要翻译： 一种3D半导体器件包括：电极结构，其具有堆叠在基板上的电极，穿透电极结构的半导体图案，插入在半导体图案和电极结构之间的电荷存储图案，以及插入在电荷存储图案和电极结构之间的绝缘图案。 每个隔离绝缘图案包围半导体图案，并且电荷存储图案彼此水平间隔并且以这样的方式配置，以使得每个隔离绝缘图案围绕相应的一个半导体图案设置。 而且，每个电荷存储图案包括多个水平段，每个水平段插入垂直相邻的电极之间。