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    Methods of manufacturing a vertical type semiconductor device
    2.
    发明授权
    Methods of manufacturing a vertical type semiconductor device 有权
    制造垂直型半导体器件的方法

    公开(公告)号：US08871591B2

    公开(公告)日：2014-10-28

    申请号：US13600025

    申请日：2012-08-30

    申请人： Yong-Hyun Kwon ,  Dae-Hyun Jang ,  Seong-Soo Lee ,  Kyoung-Sub Shin

    发明人： Yong-Hyun Kwon ,  Dae-Hyun Jang ,  Seong-Soo Lee ,  Kyoung-Sub Shin

    IPC分类号： H01L21/336

    CPC分类号： H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

    摘要： According to example embodiments of inventive concepts, a method includes forming cell patterns and insulating interlayers between the cell patterns on the substrate. An upper insulating interlayer including initial and preliminary contact holes is formed on an uppermost cell pattern. A first reflection limiting layer pattern and a first photoresist layer pattern are formed for exposing a first preliminary contact hole while covering inlet portion of the initial and preliminary contact holes. A first etching process is performed on layers under the first preliminary contact hole to expose the cell pattern at a lower position than a bottom of the first preliminary contact hole. A partial removing process of sidewall portions of the first reflection limiting layer pattern and the first photoresist layer pattern and an etching process on exposed layers through bottom portions of the preliminary contact holes are repeated for forming contact holes having different depths.

    摘要翻译： 根据本发明构思的示例性实施例，一种方法包括在基板上的单元图案之间形成单元图案和绝缘夹层。 在最上面的单元图案上形成包括初始接触孔和预接触孔的上绝缘层。 形成第一反射限制层图案和第一光致抗蚀剂层图案，用于暴露第一初步接触孔，同时覆盖初始和初步接触孔的入口部分。 在第一初步接触孔下方的层上进行第一蚀刻处理，以在比第一预接触孔的底部低的位置处露出电池图案。 重复第一反射限制层图案和第一光致抗蚀剂层图案的侧壁部分的部分去除处理以及通过预接触孔的底部的暴露层上的蚀刻工艺，以形成具有不同深度的接触孔。

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20130320486A1

    公开(公告)日：2013-12-05

    申请号：US13786853

    申请日：2013-03-06

    申请人： Jin-Hyuk YOO ,  Dae-hyun Jang ,  Yoo-Chul Kong ,  Kyoung-Sub Shin

    发明人： Jin-Hyuk YOO ,  Dae-hyun Jang ,  Yoo-Chul Kong ,  Kyoung-Sub Shin

    IPC分类号： H01L23/48

    CPC分类号： H01L27/1157 ,  H01L23/48 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.

    摘要翻译： 提供一种半导体器件。 半导体器件包括设置在半导体衬底上的导电图案。 设置在导电图案上并且彼此位于相同水平面的第一和第二导电线。 隔离图案设置在第一和第二导线之间。 提供穿过第一导线和导电图案的第一垂直结构。 提供穿过第二导线和导电图案的第二垂直结构。 提供穿过导电图案并与隔离图案接触的辅助图案。

    Method of forming active region structure
    5.
    发明授权
    Method of forming active region structure 有权
    形成有源区结构的方法

    公开(公告)号：US08420453B2

    公开(公告)日：2013-04-16

    申请号：US12801074

    申请日：2010-05-20

    申请人： Jun-Ho Yoon ,  Byeong-Soo Kim ,  Kyoung-Sub Shin ,  Hong Cho ,  Hyung-Yong Kim

    发明人： Jun-Ho Yoon ,  Byeong-Soo Kim ,  Kyoung-Sub Shin ,  Hong Cho ,  Hyung-Yong Kim

    IPC分类号： H01L21/82

    CPC分类号： H01L21/308 ,  H01L21/76229 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/11526

    摘要： A method of forming an active region structure includes preparing a semiconductor substrate including a cell array region and a peripheral circuit region, forming preliminary cell active regions in the cell array region of the semiconductor substrate, and forming cell active regions in the preliminary cell active regions and at least one peripheral active region in the peripheral circuit region of the semiconductor substrate, such that the preliminary cell active regions, the cell active regions, and the at least one peripheral active region are integrally formed with the semiconductor substrate and protrude from the semiconductor substrate.

    摘要翻译： 形成有源区结构的方法包括制备包括单元阵列区域和外围电路区域的半导体衬底，在半导体衬底的单元阵列区域中形成初级电池活性区域，并在初级电池活性区域中形成电池活性区域 以及半导体衬底的外围电路区域中的至少一个外围有源区域，使得初步电池活性区域，电池活性区域和至少一个外围有源区域与半导体衬底一体地形成并从半导体 基质。

    GATE STRUCTURES OF SEMICONDUCTOR DEVICES
    6.
    发明申请
    GATE STRUCTURES OF SEMICONDUCTOR DEVICES 审中-公开
    半导体器件的门结构

    公开(公告)号：US20100237401A1

    公开(公告)日：2010-09-23

    申请号：US12726836

    申请日：2010-03-18

    申请人： JEONG-DONG CHOE ,  Kyoung-Sub Shin ,  Kyoung-Hwan Yeo

    发明人： JEONG-DONG CHOE ,  Kyoung-Sub Shin ,  Kyoung-Hwan Yeo

    IPC分类号： H01L29/792

    CPC分类号： H01L29/792 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/513

    摘要： Gate structures of semiconductor devices and methods of forming gate structures of semiconductor devices are provided. A first insulating pattern may be disposed on an active region of a semiconductor substrate. A data storage pattern may be disposed on the first insulating pattern. A second insulating pattern may be disposed on the data storage pattern and may contact the data storage pattern. A first conductive pattern may conform to the second insulating pattern and to sidewalls of a mold comprising the second insulating pattern. A second conductive pattern may be disposed within a cavity defined by the first conductive pattern. Spacers may be formed on sidewalls of at least one of the first insulating pattern, the data storage pattern, the second insulating pattern, and the conductive pattern.

    摘要翻译： 提供了半导体器件的栅极结构和形成半导体器件的栅极结构的方法。 第一绝缘图案可以设置在半导体衬底的有源区上。 数据存储图案可以设置在第一绝缘图案上。 第二绝缘图案可以设置在数据存储图案上并且可以接触数据存储图案。 第一导电图案可以符合第二绝缘图案以及包括第二绝缘图案的模具的侧壁。 第二导电图案可以设置在由第一导电图案限定的空腔内。 间隔件可以形成在第一绝缘图案，数据存储图案，第二绝缘图案和导电图案中的至少一个的侧壁上。

    Semiconductor memory device and method of manufacturing the same
    7.
    发明授权
    Semiconductor memory device and method of manufacturing the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US06974986B2

    公开(公告)日：2005-12-13

    申请号：US10367853

    申请日：2003-02-19

    申请人： Ji-soo Kim ,  Jeong-seok Kim ,  Kyoung-sub Shin

    发明人： Ji-soo Kim ,  Jeong-seok Kim ,  Kyoung-sub Shin

    IPC分类号： H01L21/768 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

    摘要： A semiconductor memory device and manufacturing method, including a bit line connector and a lower electrode connector that respectively connect a bit line and a capacitor lower electrode of the device to active areas of a semiconductor substrate. The connectors are formed using a line-type self-aligned photoresist mask pattern positioned on an interlevel dielectric layer formed on the substrate, which exposes only a portion of the dielectric layer corresponding to a source region and which extends in a direction which a gate electrode extends, to provide a misalignment margin. The bit line connector and the lower electrode connector are respectively formed by one-time mask processes. A contact hole for the bit line connector in a cell area, and a contact hole for a metal wiring plug in a peripheral area are simultaneously formed, alleviating etching burden during subsequent forming of a metal wiring pad.

    摘要翻译： 一种半导体存储器件和制造方法，包括分别将器件的位线和电容器下电极连接到半导体衬底的有源区的位线连接器和下电极连接器。 连接器使用位于衬底上形成的层间电介质层上的线型自对准光致抗蚀剂掩模图案形成，该掩模图案仅暴露与源极区对应的介电层的一部分，并且沿栅极电极 延伸，以提供不对准余量。 位线连接器和下电极连接器分别由一次性掩模处理形成。 同时形成用于单元区域中的位线连接器的接触孔和周边区域中的金属布线插塞的接触孔，从而减轻随后形成金属布线板期间的蚀刻负担。

    Semiconductor devices having gate stack portions that extend in a zigzag pattern
    10.
    发明授权
    Semiconductor devices having gate stack portions that extend in a zigzag pattern 有权
    具有以锯齿形图案延伸的栅叠层部分的半导体器件

    公开(公告)号：US09349747B2

    公开(公告)日：2016-05-24

    申请号：US14676843

    申请日：2015-04-02

    申请人： Hyuk Kim ,  Sang Wuk Park ,  Kyoung Sub Shin

    发明人： Hyuk Kim ,  Sang Wuk Park ,  Kyoung Sub Shin

    IPC分类号： H01L27/00 ,  H01L29/00 ,  H01L27/115 ,  H01L29/792 ,  H01L29/78 ,  H01L27/02

    CPC分类号： H01L27/11582 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/7827 ,  H01L29/7831

    摘要： A semiconductor device includes a substrate having an upper surface extended in first and second directions perpendicular to each other, gate stack portions spaced apart from each other in the first direction, the gate stack portions including gate electrodes spaced apart from each other in a direction perpendicular to the an upper surface of the substrate and having lateral surfaces extended in the second direction to have a zigzag form, channel regions penetrating through the gate stack portions and disposed to form columns having a zigzag form in the second direction, at least two channel regions among the channel regions being linearly arranged in the first direction within the respective gate stack portion, and a source region disposed between the gate stack portions adjacent to each other and extended in the second direction to have a zigzag form.

    摘要翻译： 一种半导体器件包括具有在彼此垂直的第一和第二方向上延伸的上表面的基板，在第一方向上彼此间隔开的栅堆叠部分，栅堆叠部分包括在垂直方向上彼此间隔开的栅电极 并且具有在第二方向上延伸以具有锯齿形状的侧表面，通道区域穿过栅极堆叠部分并且设置成在第二方向上形成具有锯齿形状的列，至少两个沟道区域 在各栅极堆叠部分之间沿着第一方向线性排列的沟道区域和设置在彼此相邻并在第二方向上延伸以形成Z字形的栅叠层部分之间的源极区域。