公开(公告)号：US09184090B2

公开(公告)日：2015-11-10

申请号：US13151102

申请日：2011-06-01

申请人： Seung-Ha Choi ,  Kyoung-Jae Chung ,  Woo-Geun Lee

发明人： Seung-Ha Choi ,  Kyoung-Jae Chung ,  Woo-Geun Lee

IPC分类号： H01L21/00 ,  H01L21/768 ,  G02F1/1333 ,  G02F1/1362 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66

CPC分类号： H01L21/76804 ,  G02F1/133345 ,  G02F1/136227 ,  G02F1/136286 ,  H01L21/76816 ,  H01L27/1225 ,  H01L27/1244 ,  H01L27/1248 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

摘要： A TFT display panel having a high charge mobility and making it possible to obtain uniform electric characteristics with respect to a large-area display is provided as well as a manufacturing method thereof. A TFT display panel includes a gate electrode formed on an insulation substrate, a first gate insulting layer formed of SiNx on the gate electrode, a second gate insulting layer formed of SiOx on the first gate insulting layer, an oxide semiconductor layer formed to overlap the gate electrode and having a channel part, and a passivation layer formed of SiOx on the oxide semiconductor layer and the gate electrode, and the passivation layer includes a contact hole exposing the drain electrode. The contact hole has a shape in which the passivation layer of a portion directly exposed together with a metal occupies an area smaller than the upper passivation layer.

摘要翻译： 提供具有高电荷迁移率并且可以获得相对于大面积显示器的均匀电特性的TFT显示面板及其制造方法。 TFT显示面板包括形成在绝缘基板上的栅极电极，栅极上由SiNx形成的第一栅极绝缘层，在第一栅极绝缘层上由SiOx形成的第二栅极绝缘层，形成为与栅极电极重叠的氧化物半导体层 栅电极，并具有通道部分，以及由氧化物半导体层和栅电极上的SiO x形成的钝化层，钝化层包括暴露漏电极的接触孔。 接触孔具有直接与金属一起暴露的部分的钝化层占据比上钝化层小的形状。

公开(公告)号：US09059046B2

公开(公告)日：2015-06-16

申请号：US13612590

申请日：2012-09-12

申请人： Shin Il Choi ,  Seung-Ha Choi ,  Bong-Kyun Kim ,  Sang Gab Kim ,  Sho Yeon Kim ,  Hyun Kim ,  Hong Sick Park ,  Su Bin Bae

发明人： Shin Il Choi ,  Seung-Ha Choi ,  Bong-Kyun Kim ,  Sang Gab Kim ,  Sho Yeon Kim ,  Hyun Kim ,  Hong Sick Park ,  Su Bin Bae

IPC分类号： H01L29/10 ,  H01L29/12 ,  H01L27/12

CPC分类号： H01L27/1225

摘要： A thin film transistor array panel according to an exemplary embodiment of the invention includes: a substrate; a gate line positioned on the substrate and including a gate electrode; a gate insulating layer positioned on the gate line; an oxide semiconductor layer positioned on the substrate; a source electrode and a drain electrode positioned on the oxide semiconductor layer; a first insulating layer positioned on the source electrode and the drain electrode and including a first contact hole; a data line positioned on the first insulating layer and intersecting the gate line; and a pixel electrode over the first insulating layer. The source electrode and the drain electrode each comprise a metal oxide. The data line is electrically connected to the source electrode through the first contact hole.

摘要翻译： 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：基板; 位于所述基板上并包括栅电极的栅极线; 位于栅极线上的栅极绝缘层; 位于所述基板上的氧化物半导体层; 位于所述氧化物半导体层上的源电极和漏极; 位于所述源电极和所述漏极上并且包括第一接触孔的第一绝缘层; 位于所述第一绝缘层上且与所述栅极线相交的数据线; 以及在所述第一绝缘层上方的像素电极。 源电极和漏极各自包含金属氧化物。 数据线通过第一接触孔与源电极电连接。

公开(公告)号：US08994023B2

公开(公告)日：2015-03-31

申请号：US13115088

申请日：2011-05-24

申请人： Hye-Young Ryu ,  Woo-Geun Lee ,  Young-Joo Choi ,  Kyoung-Jae Chung ,  Jin-Won Lee ,  Seung-Ha Choi ,  Hee-Jun Byeon ,  Pil-Sang Yun

发明人： Hye-Young Ryu ,  Woo-Geun Lee ,  Young-Joo Choi ,  Kyoung-Jae Chung ,  Jin-Won Lee ,  Seung-Ha Choi ,  Hee-Jun Byeon ,  Pil-Sang Yun

IPC分类号： H01L47/00 ,  H01L29/10 ,  H01L29/04 ,  H01L29/15 ,  H01L27/12

CPC分类号： H01L27/1214 ,  H01L27/1225 ,  H01L27/1255

摘要： A thin film transistor array substrate capable of reducing degradation of a device due to degradation of an oxide semiconductor pattern and a method of fabricating the same are provided. The thin film transistor array substrate may include an insulating substrate on which a gate electrode is formed, a gate insulating film formed on the insulating substrate, an oxide semiconductor pattern disposed on the gate insulating film, an anti-etching pattern formed on the oxide semiconductor pattern, and a source electrode and a drain electrode formed on the anti-etching pattern. The oxide semiconductor pattern may include an edge portion positioned between the source electrode and the drain electrode, and the edge portion may include at least one conductive region and at least one non-conductive region.

摘要翻译： 提供了能够降低由于氧化物半导体图案的劣化引起的器件劣化的薄膜晶体管阵列基板及其制造方法。 薄膜晶体管阵列基板可以包括其上形成有栅极的绝缘基板，形成在绝缘基板上的栅极绝缘膜，设置在栅极绝缘膜上的氧化物半导体图案，形成在氧化物半导体上的抗蚀刻图案 图案，以及形成在防蚀刻图案上的源电极和漏电极。 氧化物半导体图案可以包括位于源电极和漏电极之间的边缘部分，并且边缘部分可以包括至少一个导电区域和至少一个非导电区域。

公开(公告)号：US20130277666A1

公开(公告)日：2013-10-24

申请号：US13612590

申请日：2012-09-12

申请人： Shin Il CHOI ,  Seung-Ha CHOI ,  Bong-Kyun KIM ,  Sang Gab KIM ,  Sho Yeon KIM ,  Hyun KIM ,  Hong Sick PARK ,  Su Bin BAE

发明人： Shin Il CHOI ,  Seung-Ha CHOI ,  Bong-Kyun KIM ,  Sang Gab KIM ,  Sho Yeon KIM ,  Hyun KIM ,  Hong Sick PARK ,  Su Bin BAE

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L27/12 ,  H01L29/24

CPC分类号： H01L27/1225

摘要： A thin film transistor array panel according to an exemplary embodiment of the invention includes: a substrate; a gate line positioned on the substrate and including a gate electrode; a gate insulating layer positioned on the gate line; an oxide semiconductor layer positioned on the substrate; a source electrode and a drain electrode positioned on the oxide semiconductor layer; a first insulating layer positioned on the source electrode and the drain electrode and including a first contact hole; a data line positioned on the first insulating layer and intersecting the gate line; and a pixel electrode over the first insulating layer. The source electrode and the drain electrode each comprise a metal oxide. The data line is electrically connected to the source electrode through the first contact hole.

摘要翻译： 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：基板; 位于所述基板上并包括栅电极的栅极线; 位于栅极线上的栅极绝缘层; 位于所述基板上的氧化物半导体层; 位于所述氧化物半导体层上的源电极和漏极; 位于所述源电极和所述漏极上并且包括第一接触孔的第一绝缘层; 位于所述第一绝缘层上且与所述栅极线相交的数据线; 以及在所述第一绝缘层上方的像素电极。 源电极和漏极各自包含金属氧化物。 数据线通过第一接触孔与源电极电连接。

公开(公告)号：US20120113346A1

公开(公告)日：2012-05-10

申请号：US13277114

申请日：2011-10-19

申请人： Seung-Ha CHOI ,  Kyoung-Jae Chung ,  Woo-Geun Lee

发明人： Seung-Ha CHOI ,  Kyoung-Jae Chung ,  Woo-Geun Lee

IPC分类号： G02F1/136 ,  H01L33/08

CPC分类号： H01L21/3086 ,  G02F1/136227 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

摘要： Provided are a display substrate, a display device, and a method of manufacturing the display substrate. The display substrate includes: a substrate in which a pixel region is defined; a gate electrode and a gate pad are formed on the substrate; a gate insulating layer formed on the gate electrode and the gate pad; a buffer layer pattern overlaps the gate electrode and is formed on the gate insulating layer; an insulating film pattern formed on the buffer layer pattern; an oxide semiconductor pattern formed on the insulating film pattern; a source electrode formed on the oxide semiconductor pattern; and a drain electrode formed on the oxide semiconductor pattern and is separated from the source electrode.

摘要翻译： 提供了显示基板，显示装置和制造显示基板的方法。 显示基板包括：限定像素区域的基板; 在基板上形成栅电极和栅极焊盘; 形成在栅极电极和栅极焊盘上的栅极绝缘层; 缓冲层图案与栅电极重叠并形成在栅极绝缘层上; 形成在缓冲层图案上的绝缘膜图案; 形成在所述绝缘膜图案上的氧化物半导体图案; 形成在所述氧化物半导体图案上的源电极; 以及形成在氧化物半导体图案上并与源电极分离的漏电极。

公开(公告)号：US20110297931A1

公开(公告)日：2011-12-08

申请号：US13210282

申请日：2011-08-15

申请人： Dong-Ju YANG ,  Yu-Gwang JEONG ,  Ki-Yeup LEE ,  Sang-Gab KIM ,  Yun-Jong YEO ,  Shin-Il CHOI ,  Hong-Kee CHIN ,  Seung-Ha CHOI ,  Jung-Suk BANG

发明人： Dong-Ju YANG ,  Yu-Gwang JEONG ,  Ki-Yeup LEE ,  Sang-Gab KIM ,  Yun-Jong YEO ,  Shin-Il CHOI ,  Hong-Kee CHIN ,  Seung-Ha CHOI ,  Jung-Suk BANG

IPC分类号： H01L29/786

CPC分类号： H01L27/1248 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/7869

摘要： A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.

摘要翻译： 提出了制造薄膜晶体管阵列基板的方法。 该方法需要在绝缘基板上形成栅极互连线，在栅极互连线上形成栅极绝缘层，在半导体层上形成半导体层和数据互连线，依次形成多个钝化层，将钝化层蚀刻到 作为数据互连线的延伸线的漏电极。 在该阶段暴露的漏电极的部分是漏极电极 - 像素电极接触部分的一部分。 形成连接到漏电极的像素电极。 两个钝化层具有相同的组成，但是在不同的温度下进行处理。 还提出了以上述方式制备的薄膜晶体管。

公开(公告)号：US08017459B2

公开(公告)日：2011-09-13

申请号：US12484116

申请日：2009-06-12

申请人： Dong-Ju Yang ,  Yu-Gwang Jeong ,  Ki-Yeup Lee ,  Sang-Gab Kim ,  Yun-Jong Yeo ,  Shin-Il Choi ,  Hong-Kee Chin ,  Seung-Ha Choi ,  Jung-Suk Bang

发明人： Dong-Ju Yang ,  Yu-Gwang Jeong ,  Ki-Yeup Lee ,  Sang-Gab Kim ,  Yun-Jong Yeo ,  Shin-Il Choi ,  Hong-Kee Chin ,  Seung-Ha Choi ,  Jung-Suk Bang

IPC分类号： H01L21/00

CPC分类号： H01L27/1248 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/7869

摘要： A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.

摘要翻译： 提出了制造薄膜晶体管阵列基板的方法。 该方法需要在绝缘基板上形成栅极互连线，在栅极互连线上形成栅极绝缘层，在半导体层上形成半导体层和数据互连线，依次形成多个钝化层，将钝化层蚀刻到 作为数据互连线的延伸线的漏电极。 在该阶段暴露的漏电极的部分是漏极电极 - 像素电极接触部分的一部分。 形成连接到漏电极的像素电极。 两个钝化层具有相同的组成，但是在不同的温度下进行处理。 还提出了以上述方式制备的薄膜晶体管。

公开(公告)号：US20110114940A1

公开(公告)日：2011-05-19

申请号：US12818047

申请日：2010-06-17

申请人： Do-Hyun Kim ,  Kyoung-Jae Chung ,  Seung-Ha Choi ,  Dong-Hoon Lee ,  Chang-Oh Jeong ,  Suk-Won Jung

发明人： Do-Hyun Kim ,  Kyoung-Jae Chung ,  Seung-Ha Choi ,  Dong-Hoon Lee ,  Chang-Oh Jeong ,  Suk-Won Jung

IPC分类号： H01L29/786 ,  H01L21/36

CPC分类号： H01L27/1225 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02664 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3262

摘要： A thin film transistor array panel includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a gate insulating layer disposed on the gate line; an semiconductive oxide layer disposed on the gate insulating layer; a data line disposed on the semiconductive oxide layer and including a source electrode; a drain electrode facing the source electrode on the semiconductive oxide layer; and a passivation layer disposed on the data line. The semiconductive oxide layer is patterned with chlorine (Cl) containing gas which alters relative atomic concentrations of primary semiconductive characteristic-providing elements of the semiconductive oxide layer at least at a portion where a transistor channel region is defined.

摘要翻译： 薄膜晶体管阵列面板包括：基板; 栅极线，设置在所述基板上并且包括栅电极; 设置在栅极线上的栅极绝缘层; 设置在所述栅极绝缘层上的半导体氧化物层; 数据线，设置在所述半导体氧化物层上并包括源电极; 在半导体氧化物层上面对源电极的漏电极; 以及设置在数据线上的钝化层。 至少在限定了晶体管沟道区域的部分，半导体氧化物层用含氯（Cl）的气体构图，该气体改变半导体氧化物层的初级半导体特性提供元件的相对原子浓度。

公开(公告)号：US07638375B2

公开(公告)日：2009-12-29

申请号：US12009253

申请日：2008-01-16

申请人： Hong-Kee Chin ,  Yu-Gwang Jeong ,  Sang-Gab Kim ,  Joo-Han Kim ,  Joo-Ae Youn ,  Min-Seok Oh ,  Jong-Hyun Choung ,  Seung-Ha Choi

发明人： Hong-Kee Chin ,  Yu-Gwang Jeong ,  Sang-Gab Kim ,  Joo-Han Kim ,  Joo-Ae Youn ,  Min-Seok Oh ,  Jong-Hyun Choung ,  Seung-Ha Choi

IPC分类号： H01L21/84

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： A method of manufacturing a TFT substrate includes: sequentially forming a transparent conductive layer and an opaque conductive layer on a substrate, patterning the transparent conductive layer and the opaque conductive layer by using a first mask to form a gate pattern including a pixel electrode, and forming a gate insulating layer and a semiconductor layer above the substrate. A contact hole is formed which exposes a portion of the pixel electrode and a semiconductor pattern using a second mask. A conductive layer is formed above the substrate and patterned to form a source/drain pattern including a drain electrode which overlaps a portion of the pixel electrode. Portions of the gate insulating layer and the opaque conductive layer above the pixel electrode are removed except a portion overlapping the drain electrode, by using a third mask.

摘要翻译： 一种制造TFT基板的方法包括：在基板上依次形成透明导电层和不透明导电层，通过使用第一掩模对透明导电层和不透明导电层进行构图，形成包括像素电极的栅极图案，以及 在基板上形成栅极绝缘层和半导体层。 使用第二掩模形成露出一部分像素电极和半导体图案的接触孔。 在衬底上形成导电层，并被图案化以形成包括与像素电极的一部分重叠的漏电极的源极/漏极图案。 除了与漏电极重叠的部分之外，通过使用第三掩模除去栅极绝缘层和像素电极上方的不透明导电层的部分。

公开(公告)号：US20080280379A1

公开(公告)日：2008-11-13

申请号：US11933413

申请日：2007-10-31

申请人： Min-Seok OH ,  Sang-Gab KIM ,  Hong-Kee CHIN ,  Yu-Gwang JEONG ,  Seung-Ha CHOI ,  Ki-Hyun KIM ,  In-Ho SONG

发明人： Min-Seok OH ,  Sang-Gab KIM ,  Hong-Kee CHIN ,  Yu-Gwang JEONG ,  Seung-Ha CHOI ,  Ki-Hyun KIM ,  In-Ho SONG

IPC分类号： H01L21/66 ,  H01L21/67

CPC分类号： H01L22/12 ,  H01L27/1288 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a method of manufacturing a thin film transistor substrate and a manufacturing system using the same, wherein the production of corrosive substances is reduced during the process of manufacturing the thin film transistor substrate. The method includes providing an etching unit with an insulation substrate on which a thin metal film has been deposited, and dry-etching the insulation substrate so as to form a predetermined circuit pattern; providing a waiting unit with the insulation substrate waiting to be cleaned; performing a preliminary cleaning operation by a cleaning unit having a plurality of nozzles while the insulation substrate waits and checking the preliminary cleaning operation; and performing a main cleaning operation with regard to the insulation substrate based on the result of the check.

摘要翻译： 提供一种制造薄膜晶体管基板的方法和使用该薄膜晶体管基板的制造系统，其中在制造薄膜晶体管基板的过程中，腐蚀性物质的产生减少。 该方法包括：提供具有绝缘基板的蚀刻单元，在其上沉积有薄金属膜，并对绝缘基板进行干蚀刻以形成预定的电路图案; 提供等待单元与等待清理的绝缘基板; 在绝缘基板等待并检查预备清洗操作的同时，通过具有多个喷嘴的清洗单元执行初步清洁操作; 并且基于检查结果对绝缘基板进行主清洗操作。