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    Integrated Circuit With A Trench Capacitor Structure And Method Of Manufacture
    4.
    发明申请
    Integrated Circuit With A Trench Capacitor Structure And Method Of Manufacture 失效
    具有沟槽电容器结构的集成电路和制造方法

    公开(公告)号：US20070267670A1

    公开(公告)日：2007-11-22

    申请号：US11383670

    申请日：2006-05-16

    申请人： Sailesh Chittipeddi ,  Seungmoo Choi

    发明人： Sailesh Chittipeddi ,  Seungmoo Choi

    IPC分类号： H01L29/94

    CPC分类号： H01L28/40 ,  H01L27/1087 ,  H01L27/11

    摘要： An integrated circuit device having a capacitor structure. In one form of the invention, an integrated circuit device includes a capacitor structure formed along a surface of a semiconductor layer. The capacitor structure includes a trench region formed in the semiconductor surface, a layer of dielectric material formed along a wall of the trench region and a first layer of doped polysilicon formed over the layer of dielectric material in the trench region. The capacitor structure further includes a second layer of doped polysilicon formed over the first layer of polysilicon.

    摘要翻译： 一种具有电容器结构的集成电路器件。 在本发明的一种形式中，集成电路器件包括沿着半导体层的表面形成的电容器结构。 电容器结构包括形成在半导体表面中的沟槽区域，沿着沟槽区域的壁形成的电介质材料层，以及形成在沟槽区域中的电介质材料层上的第一掺杂多晶硅层。 电容器结构还包括形成在第一多晶硅层上的第二掺杂多晶硅层。

    Multiple purpose reticle layout for selective printing of test circuits
    5.
    发明授权
    Multiple purpose reticle layout for selective printing of test circuits 失效
    用于选择性打印测试电路的多用途标线布局

    公开(公告)号：US06893806B2

    公开(公告)日：2005-05-17

    申请号：US10219951

    申请日：2002-08-15

    申请人： Cheryl Anne Bollinger ,  Seungmoo Choi ,  William T. Cochran ,  Stephen Arlon Meisner ,  Daniel Mark Wroge ,  Gerard Zaneski

    发明人： Cheryl Anne Bollinger ,  Seungmoo Choi ,  William T. Cochran ,  Stephen Arlon Meisner ,  Daniel Mark Wroge ,  Gerard Zaneski

    IPC分类号： G03F1/00 ,  G03F7/20 ,  G03F9/00

    CPC分类号： G03F7/70433 ,  G03F1/44

    摘要： A method for manufacturing a semiconductor wafer uses a reticle having a plurality of spaced apart circuit images of identical patterns or images of a common level of a single integrated circuit formed on the reticle and arranged in columns and rows about its central point. At least one column of spaced apart test images are formed outside of and adjacent an outermost column of circuit images. Radiation is projected through the reticle for exposing the patterns on the reticle onto an underlying wafer. A reticle holder having a pair of shutter elements aligned parallel to the columns of images selectively blocks the projection of radiation through the columns of the test images but are exposed in order to form test circuits on the wafer at selected locations.

    摘要翻译： 半导体晶片的制造方法使用具有相同图案的多个间隔开的电路图像的掩模版，所述电路图像形成在所述掩模版上并形成在其中心点上的列和列中的单个集成电路的共同电平的图像。 至少一列间隔开的测试图像形成在电路图像的最外面的一列之外并与其相邻。 通过掩模版投影辐射，将掩模版上的图案暴露在下面的晶片上。 具有平行于图像列排列的一对快门元件的光罩保持器选择性地阻挡辐射通过测试图像的列的投影，但是暴露以便在选定位置在晶片上形成测试电路。

    Contactless local interconnect process utilizing self-aligned silicide
    6.
    发明授权
    Contactless local interconnect process utilizing self-aligned silicide 失效
    使用自对准硅化物的非接触式局部互连工艺

    公开(公告)号：US06468899B1

    公开(公告)日：2002-10-22

    申请号：US09893078

    申请日：2001-06-27

    申请人： Seungmoo Choi

    发明人： Seungmoo Choi

    IPC分类号： H01L214763

    CPC分类号： H01L21/76895 ,  H01L21/28518

    摘要： A contactless, self-aligned local interconnect structure provides a continuous silicide film electrically coupling an upper silicon structure to a lower silicon structure. The upper silicon structure overlaps the lower silicon structure and is insulated from the lower silicon structure by an insulating layer formed between the structures. The continuous silicide film electrically couples the two structures by bridging the gap formed by the insulating layer in the overlap region. The associated process for forming the local interconnect structure includes forming a lateral edge of the upper silicon structure extending over the lower silicon structure, forming a blanket metal film, then heating the metal film such that the metal film reacts with the exposed silicon of the upper silicon structure and the lower silicon structure to form a continuous silicide film which bridges the gap formed by the insulating layer which is formed of a thickness chosen to be suitably low. After the silicide film is formed, unreacted portions of the metal film are removed.

    摘要翻译： 非接触式自对准局部互连结构提供了将上硅结构电连接到较低硅结构的连续硅化物膜。 上硅结构与下硅结构重叠，并且通过在结构之间形成的绝缘层与下硅结构绝缘。 连续硅化物膜通过桥接由重叠区域中的绝缘层形成的间隙来电耦合两个结构。 用于形成局部互连结构的相关联的工艺包括形成延伸在下硅结构上的上硅结构的横向边缘，形成覆盖金属膜，然后加热金属膜，使得金属膜与上部的硅的暴露的硅反应 硅结构和较低的硅结构以形成连接的硅化物膜，其桥接由选择为适当低的厚度形成的绝缘层形成的间隙。 在形成硅化物膜之后，除去金属膜的未反应部分。

    Vertical DRAM device with channel access transistor and stacked storage capacitor and associated method
    9.
    发明授权
    Vertical DRAM device with channel access transistor and stacked storage capacitor and associated method 有权
    具有通道存取晶体管和堆叠存储电容器的垂直DRAM器件及相关方法

    公开(公告)号：US06603168B1

    公开(公告)日：2003-08-05

    申请号：US09553868

    申请日：2000-04-20

    申请人： Seungmoo Choi

    发明人： Seungmoo Choi

    IPC分类号： H01L27108

    CPC分类号： H01L29/7827 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/42356 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit memory device includes a substrate having at least one connection line therein and a plurality of memory cells formed on the substrate. Each memory cell includes a pillar comprising a lower source/drain region for a cell access transistor electrically connected to the connection line, an upper source/drain region for the cell access transistor, and at least one channel region extending vertically between the lower and upper source/drain regions. Each memory cell further includes at least one lower dielectric layer vertically adjacent the substrate and laterally adjacent the pillar and at least one upper dielectric layer vertically spaced above the at least one lower dielectric layer and laterally adjacent the pillar. Further, each memory cell includes at least one gate for the at least one channel of the cell access transistor between the lower and upper dielectric layers so that the vertical spacing therebetween defines a gate length for the cell access transistor. A storage capacitor is also included in each memory cell adjacent the upper source/drain region of the cell access transistor and is electrically connected thereto.

    摘要翻译： 集成电路存储器件包括其中具有至少一个连接线的衬底和形成在衬底上的多个存储单元。 每个存储单元包括一个柱，该柱包括一个电连接到该连接线的单元存取晶体管的下部源极/漏极区域，一个用于该单元存取晶体管的上部源极/漏极区域，以及至少一个在下部和上部之间垂直延伸的沟道区域 源/漏区。 每个存储单元还包括垂直邻近衬底并且横向邻近柱的至少一个下介电层和垂直间隔在至少一个下电介质层上方并且横向邻近柱的至少一个上电介质层。 此外，每个存储单元包括至少一个用于在下介电层和上介电层之间的单元存取晶体管的至少一个通道的栅极，使得其间的垂直间隔限定了用于单元存取晶体管的栅极长度。 存储电容器还包括在与单元存取晶体管的上部源极/漏极区域相邻的每个存储单元中，并与其电连接。

    Device and method for forming semiconductor interconnections in an integrated circuit substrate
    10.
    发明授权
    Device and method for forming semiconductor interconnections in an integrated circuit substrate 有权
    在集成电路基板中形成半导体互连的装置和方法

    公开(公告)号：US06503787B1

    公开(公告)日：2003-01-07

    申请号：US09631546

    申请日：2000-08-03

    申请人： Seungmoo Choi

    发明人： Seungmoo Choi

    IPC分类号： H01L218238

    CPC分类号： H01L21/823475 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a semiconductor device, formed on a semiconductor wafer, comprising a tub, first and second active areas, and an interconnect. In one aspect of the present invention, the tub is formed in the substrate of the semiconductor wafer and first and second active areas are in contact with the tub. In one advantageous embodiment, the interconnect is formed in the tub and is in electrical contact with the first and second active areas. The interconnect extends from the first active area to the second active area to electrically connect the first and second active areas.

    摘要翻译： 本发明提供一种形成在半导体晶片上的半导体器件，包括一个第一和第二有源区以及互连。 在本发明的一个方面，在半导体晶片的衬底中形成桶，并且第一和第二有源区与桶接触。 在一个有利的实施例中，互连件形成在桶中并且与第一和第二有效区域电接触。 互连从第一有源区延伸到第二有源区，以电连接第一和第二有源区。