公开(公告)号：US5841186A

公开(公告)日：1998-11-24

申请号：US912867

申请日：1997-08-19

申请人： Shi-Chung Sun ,  Tsai-Fu Chen

发明人： Shi-Chung Sun ,  Tsai-Fu Chen

IPC分类号： H01L21/02 ,  H01L23/58

CPC分类号： H01L28/40

摘要： Composite TiO.sub.2 /Ta.sub.2 O.sub.5 films by in-situ sequential CVD deposition are presented for a storage capacitor of a three-dimensional cell in DRAM applications. The capacitor with the Ta.sub.2 O.sub.5 /TiO.sub.2 /Ta.sub.2 O.sub.5 alternating layer structure has comparable leakage current density and higher capacitance per unit area as compared to a capacitor with Ta.sub.2 O.sub.5 and TiO.sub.2 single layer structures.

摘要翻译： 在DRAM应用中，提出了通过原位顺序CVD沉积的复合TiO 2 / Ta 2 O 5膜用于三维单元的存储电容器。 与Ta2O5和TiO2单层结构的电容器相比，具有Ta2O5 / TiO2 / Ta2O5交替层结构的电容器具有相当的漏电流密度和每单位面积的较高电容。

公开(公告)号：US06624073B2

公开(公告)日：2003-09-23

申请号：US09999453

申请日：2001-12-03

申请人： Shi-Chung Sun ,  Hao-Yi Tsai

发明人： Shi-Chung Sun ,  Hao-Yi Tsai

IPC分类号： C23C1434

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76864 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A new method of forming a tantalum carbide nitride diffusion barrier layer having optimized nitrogen concentration for improved thermal stability is described. A contact region is provided in a substrate. A via is opened through an insulating layer to the contact region. A tantalum carbide nitride barrier layer is deposited within the via wherein the tantalum carbide nitride layer has an optimized nitrogen content of between about 17% and 24% by atomic percentage. A layer of copper is deposited overlying the tantalum carbide nitride barrier layer to complete copper metallization in the fabrication of an integrated circuit device.

公开(公告)号：US5880040A

公开(公告)日：1999-03-09

申请号：US632178

申请日：1996-04-15

申请人： Shi-Chung Sun ,  Chun-Hon Chen ,  Lee-Wei Yen ,  Chun-Jung Lin

发明人： Shi-Chung Sun ,  Chun-Hon Chen ,  Lee-Wei Yen ,  Chun-Jung Lin

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/316

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L29/518

摘要： A new technique for the formation of high quality ultrathin gate dielectrics is proposed. Gate oxynitride was first grown in N.sub.2 O and then annealed by in-situ rapid thermal NO-nitridation. This approach has the advantage of providing a tighter nitrogen distribution and a higher nitrogen accumulation at or near the Si--SiO.sub.2 interface than either N.sub.2 O oxynitride or nitridation of SiO.sub.2 in the NO ambient. It is applicable to a wide range of oxide thickness because the initial rapid thermal N.sub.2 O oxidation rate is slow but not as self-limited as NO oxidation. The resulting gate dielectrics have reduced charge trapping, lower stress-induced leakage current and significant resistance to interface state generation under electrical stress.

摘要翻译： 提出了一种形成高质量超薄栅极电介质的新技术。 氮氧化物首先在N2O中生长，然后通过原位快速热NO氮化退火。 这种方法的优点是在NO环境中提供比N2O氮氧化合物或SiO 2的氮化作用更严格的氮分布和在Si-SiO 2界面处或附近的更高的氮积累。 它适用于广泛的氧化物厚度，因为初始快速热氧化N2O氧化速率慢但不像NO氧化那样自限制。 所得到的栅极电介质具有减少的电荷捕获，较低的应力诱发的漏电流和对电应力下的界面状态产生的显着阻力。

公开(公告)号：US5668054A

公开(公告)日：1997-09-16

申请号：US584749

申请日：1996-01-11

申请人： Shi-Chung Sun ,  Hien-Tien Chiu ,  Ming-Hsing Tsai

发明人： Shi-Chung Sun ,  Hien-Tien Chiu ,  Ming-Hsing Tsai

IPC分类号： C23C16/34 ,  H01L21/285 ,  H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76843 ,  C23C16/34 ,  H01L21/28556

摘要： A process for fabricating a tantalum nitride diffusion barrier for the advanced copper metallization of semiconductor devices is disclosed. The process comprises the steps of first preparing a semiconductor device fabricated over the surface of a silicon substrate having a component with a fabricated contact opening. Before the formation of the copper contact by deposition, the process performs a tantalum nitride low-pressure chemical-vapor-deposition procedure that deposits a layer of tantalum nitride thin film over the surface of the device substrate. After the copper deposition, a photoresist layer is subsequently fabricated for patterning the deposited copper contact and tantalum nitride layers, whereby the deposited thin film of tantalum nitride is patterned to form the thin film as the metallization diffusion barrier for the semiconductor device. The tantalum nitride low-pressure chemical-vapor-deposition procedure includes depositing a layer of tantalum nitride utilizing a metal-organic precursor terbutylimido-tris-diethylamido tantalum (TBTDET) in a cold-wall low pressure reactor with a base pressure of about 10.sup.-5 torr. The source of the metal-organic precursor is vaporized at a temperature of about 40.degree. to 50.degree. C. The typical deposition pressure is about 20 mtorr. Tantalum nitride layer of low carbon content and low resistivity may thus be formed in the disclosed chemical-vapor-deposition procedure having effective capability against copper diffusion.

摘要翻译： 公开了一种用于制造用于半导体器件的先进铜金属化的氮化钽扩散阻挡层的工艺。 该方法包括以下步骤：首先制备在具有制造的接触开口的部件的硅衬底的表面上制造的半导体器件。 在通过沉积形成铜接触之前，该工艺执行在器件衬底的表面上沉积氮化钽薄层的氮化钽低压化学气相沉积工艺。 在铜沉积之后，随后制造光致抗蚀剂层以图案化沉积的铜接触和氮化钽层，由此沉积的氮化钽薄膜被图案化以形成作为半导体器件的金属化扩散阻挡层的薄膜。 氮化钽低压化学气相沉积方法包括使用金属有机前体叔丁基亚氨基 - 三 - 二乙基氨基钽（TBTDET）在基本压力为约10 -6的冷壁低压反应器中沉积氮化钽层， 5托 金属有机前体的来源在约40℃至50℃的温度下蒸发。典型的沉积压力为约20毫托。 因此，可以在具有对铜扩散的有效能力的公开的化学气相沉积方法中形成低碳含量和低电阻率的氮化钽层。

公开(公告)号：US06359160B1

公开(公告)日：2002-03-19

申请号：US09590123

申请日：2000-06-09

申请人： Shi-Chung Sun ,  Hien-Tien Chiu

发明人： Shi-Chung Sun ,  Hien-Tien Chiu

IPC分类号： C07F1100

CPC分类号： H01L21/76856 ,  C23C16/34 ,  H01L21/28556 ,  H01L21/76843

摘要： A new method of forming a molybdenum nitride barrier layer by chemical vapor deposition from the precursor bisdiethylamido-bistertbutylimido-molybdenum (BDBTM) as a diffusion barrier for copper metallization is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is deposited overlying the sermiconductor device structures. A via opening is etched through the insulating layer to contact one of the semiconductor device structures. A barrier layer of molybdenum nitride is conformally deposited by chemical vapor deposition within the via. A layer of copper is deposited overlying the molybdenum nitride barrier layer wherein the molybdenum nitride barrier layer prevents copper diffusion to complete the copper metallization in the fabrication of an integrated circuit device.

摘要翻译： 描述了通过化学气相沉积从作为铜金属化的扩散阻挡层的前体双二乙基氨基 - 二乙基亚胺基 - 钼（BDBTM）形成氮化钼阻挡层的新方法。 半导体器件结构设置在半导体衬底中和半导体衬底上。 绝缘层沉积在半导体器件结构上。 通孔绝缘层被蚀刻以接触半导体器件结构之一。 通过化学气相沉积在通孔内共形沉积氮化钼的阻挡层。 覆盖氮化钼阻挡层上的一层铜沉积，其中氮化钼阻挡层在制造集成电路器件时防止铜扩散完成铜金属化。

公开(公告)号：US06294819B1

公开(公告)日：2001-09-25

申请号：US09679511

申请日：2000-10-06

申请人： Shi-Chung Sun

发明人： Shi-Chung Sun

IPC分类号： H01L2972

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method of fabricating a CVD Ta2O5/Oxynitride stacked gate insulator with TiN gate electrode for subquarter micron MOSFETs is disclosed. In a first embodiment, the surface of a silicon substrate is reacted in N2O or NC ambient to form an oxynitride layer. Tantalum oxide is next chemical vapor deposited, thus forming a Ta2O5/Oxynitride stacked gate insulator. The stacked gate is then completed by depositing titanium nitride as the gate electrode and then patterning and forming the gate structure. In the second embodiment, a gate oxide is first formed on the silicon substrate. Then the gate oxide layer is nitridated in N2O or NO ambient to form the oxynitridated layer, thus forming a two-step oxynitride layer. The tantalum oxide layer and the titanium nitride gate electrode are formed as in the first embodiment. It is disclosed in the present invention that by replacing the conventional SiO2 layer with a composite layer of Ta2O5/oxynitride, where the oxynitride dielectric layer is grown in a nitrogen ambient, charge trapping, interface state generation, and breakdown field distribution, the time-dependent dielectric breakdown (TDDB) of gate oxides and hence the reliability of MOSFET devices are improved substantially.

摘要翻译： 公开了一种制造具有用于亚微米级MOSFET的TiN栅电极的CVD Ta2O5 /氮氧化物层叠栅极绝缘体的方法。 在第一实施例中，硅衬底的表面在N2O或NC环境中反应以形成氧氮化物层。 接着化学气相沉积氧化钽，从而形成Ta2O5 /氮氧化物层叠栅极绝缘体。 然后通过沉积氮化钛作为栅电极，然后构图和形成栅极结构来完成堆叠的栅极。 在第二实施例中，首先在硅衬底上形成栅极氧化物。 然后将栅极氧化物层在N 2 O或NO环境中氮化，形成氧化氮化层，形成两步氮氧化物层。 如第一实施例中那样形成氧化钽层和氮化钛栅电极。 在本发明中公开了通过用氮氧化合物中的氮氧化物电介质层生长的电荷捕获，界面状态产生和击穿场分布来替代传统的SiO 2层与Ta 2 O 5 /氮氧化物的复合层， 栅极氧化物的相关介质击穿（TDDB），从而提高MOSFET器件的可靠性。

公开(公告)号：US06171900B2

公开(公告)日：2001-01-09

申请号：US09292354

申请日：1999-04-15

申请人： Shi-Chung Sun

发明人： Shi-Chung Sun

IPC分类号： H01L218242

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method of fabricating a CVD Ta2O5/Oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFETs is disclosed. In a first embodiment, the surface of a silicon substrate is reacted in N2O or NO ambient to form an oxynitride layer. Tantalum oxide is next chemical vapor deposited, thus forming a Ta2O5/Oxynitride stacked gate insulator. The stacked gate is then completed by depositing titanium nitride as the gate electrode and then patterning and forming the gate structure. In the second embodiment, a gate oxide is first formed on the silicon substrate. Then the gate oxide layer is nitridated in N2O or NO ambient to form the oxynitridated layer, thus forming a two-step oxynitride layer. The tantalum oxide layer and the titanium nitride gate electrode are formed as in the first embodiment. It is disclosed in the present invention that by replacing the conventional SiO2 layer with a composite layer of Ta2O5/oxynitride, where the oxynitride dielectric layer is grown in a nitrogen ambient, charge trapping, interface state generation, and breakdown field distribution, the time-dependent dielectric breakdown (TDDB) of gate oxides and hence the reliability of MOSFET devices are improved substantially.

摘要翻译： 公开了一种制造具有用于二分之一微米MOSFET的TiN栅电极的CVD Ta2O5 /氮氧化物层叠栅极绝缘体的方法。 在第一实施例中，硅衬底的表面在N 2 O或NO环境中反应以形成氧氮化物层。 接着化学气相沉积氧化钽，从而形成Ta2O5 /氮氧化物层叠栅极绝缘体。 然后通过沉积氮化钛作为栅电极，然后构图和形成栅极结构来完成堆叠的栅极。 在第二实施例中，首先在硅衬底上形成栅极氧化物。 然后将栅极氧化物层在N 2 O或NO环境中氮化，形成氧化氮化层，形成两步氮氧化物层。 如第一实施例中那样形成氧化钽层和氮化钛栅电极。 在本发明中公开了通过用氮氧化合物中的氮氧化物电介质层生长的电荷捕获，界面状态产生和击穿场分布来替代传统的SiO 2层与Ta 2 O 5 /氮氧化物的复合层， 栅极氧化物的相关介质击穿（TDDB），从而提高MOSFET器件的可靠性。

公开(公告)号：US5930584A

公开(公告)日：1999-07-27

申请号：US640085

申请日：1996-04-30

申请人： Shi-Chung Sun ,  Tsai-Fu Chen

发明人： Shi-Chung Sun ,  Tsai-Fu Chen

IPC分类号： C23C16/40 ,  C23C16/02 ,  C23C16/56 ,  H01G4/33 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/302

CPC分类号： H01L21/31604 ,  C23C16/0218 ,  C23C16/405 ,  C23C16/56

摘要： A process for fabricating electrodes for the capacitor dielectric of semiconductor memory devices with low leakage current characteristics is disclosed. The process comprises the steps of first depositing a titanium oxide film over a semiconductor silicon substrate. The deposited titanium oxide film is then annealed. A layer of tungsten nitride top electrode is then deposited on the annealed titanium oxide film. A second annealing procedure is then conducted to simulate post electrode high temperature process.

摘要翻译： 公开了一种用于制造具有低漏电流特性的半导体存储器件的电容器电介质的电极的工艺。 该方法包括首先在半导体硅衬底上沉积氧化钛膜的步骤。 然后将沉积的氧化钛膜退火。 然后在退火的氧化钛膜上沉积一层氮化钨顶电极。 然后进行第二退火程序以模拟后电极高温工艺。

公开(公告)号：US06150209A

公开(公告)日：2000-11-21

申请号：US298451

申请日：1999-04-23

申请人： Shi-Chung Sun ,  Jiann-Shing Lee

发明人： Shi-Chung Sun ,  Jiann-Shing Lee

IPC分类号： H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242

CPC分类号： H01L28/40 ,  H01L21/31604 ,  H01L27/10852

摘要： A process of fabricating a capacitor structure, using a tantalum oxide capacitor dielectric layer, has been developed. The process features deposition of a thin, high dielectric constant tantalum oxide layer, followed by a high density plasma anneal procedure, used to reduce the leakage current in the as-deposited tantalum oxide layer, that can evolve during normal operating conditions of the capacitor structure. The high density plasma anneal procedure is performed in a nitrous oxide ambient, at a temperature of about 400.degree. C.

摘要翻译： 已经开发了使用钽氧化物电容器电介质层制造电容器结构的工艺。 该工艺特征是沉积薄的高介电常数钽氧化物层，随后是高密度等离子体退火工艺，用于减少在沉积的氧化钽层中的漏电流，这可以在电容器结构的正常工作条件下演化 。 高密度等离子体退火工艺在一氧化二氮环境中，在约400℃的温度下进行

公开(公告)号：US6114242A

公开(公告)日：2000-09-05

申请号：US985404

申请日：1997-12-05

申请人： Shi-Chung Sun ,  Hien-Tien Chiu

发明人： Shi-Chung Sun ,  Hien-Tien Chiu

IPC分类号： C23C16/34 ,  H01L21/285 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76856 ,  C23C16/34 ,  H01L21/28556 ,  H01L21/76843

摘要： A new method of forming a molybdenum nitride barrier layer by chemical vapor deposition from the precursor bisdiethylamido-bistertbutylimido-molybdenum (BDBTM) as a diffusion barrier for copper metallization is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is deposited overlying the semiconductor devise structures. A via opening is etched through the insulating layer to contact one of the semiconductor device structures. A barrier layer of molybdenum nitride is conformally deposited by chemical vapor deposition within the via. A layer of copper is deposited overlying the molybdenum nitride barrier layer wherein the molybdenum nitride barrier layer prevents copper diffusion to complete the copper metallization in the fabrication of an integrated circuit device.

摘要翻译： 描述了通过化学气相沉积从作为铜金属化的扩散阻挡层的前体双二乙基氨基 - 二乙基亚胺基 - 钼（BDBTM）形成氮化钼阻挡层的新方法。 半导体器件结构设置在半导体衬底中和半导体衬底上。 绝缘层沉积在半导体器件结构上。 通孔绝缘层被蚀刻以接触半导体器件结构之一。 通过化学气相沉积在通孔内共形沉积氮化钼的阻挡层。 覆盖氮化钼阻挡层上的一层铜沉积，其中氮化钼阻挡层在制造集成电路器件时防止铜扩散完成铜金属化。