公开(公告)号：US5880040A

公开(公告)日：1999-03-09

申请号：US632178

申请日：1996-04-15

申请人： Shi-Chung Sun ,  Chun-Hon Chen ,  Lee-Wei Yen ,  Chun-Jung Lin

发明人： Shi-Chung Sun ,  Chun-Hon Chen ,  Lee-Wei Yen ,  Chun-Jung Lin

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/316

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L29/518

摘要： A new technique for the formation of high quality ultrathin gate dielectrics is proposed. Gate oxynitride was first grown in N.sub.2 O and then annealed by in-situ rapid thermal NO-nitridation. This approach has the advantage of providing a tighter nitrogen distribution and a higher nitrogen accumulation at or near the Si--SiO.sub.2 interface than either N.sub.2 O oxynitride or nitridation of SiO.sub.2 in the NO ambient. It is applicable to a wide range of oxide thickness because the initial rapid thermal N.sub.2 O oxidation rate is slow but not as self-limited as NO oxidation. The resulting gate dielectrics have reduced charge trapping, lower stress-induced leakage current and significant resistance to interface state generation under electrical stress.

摘要翻译： 提出了一种形成高质量超薄栅极电介质的新技术。 氮氧化物首先在N2O中生长，然后通过原位快速热NO氮化退火。 这种方法的优点是在NO环境中提供比N2O氮氧化合物或SiO 2的氮化作用更严格的氮分布和在Si-SiO 2界面处或附近的更高的氮积累。 它适用于广泛的氧化物厚度，因为初始快速热氧化N2O氧化速率慢但不像NO氧化那样自限制。 所得到的栅极电介质具有减少的电荷捕获，较低的应力诱发的漏电流和对电应力下的界面状态产生的显着阻力。

公开(公告)号：US06734079B2

公开(公告)日：2004-05-11

申请号：US10170840

申请日：2002-06-13

申请人： Chi-Feng Huang ,  Shyh-Chyi Wang ,  Chih-Hsien Lin ,  Chun-Hon Chen ,  Tien-I Bao ,  Syun-Ming Jang

发明人： Chi-Feng Huang ,  Shyh-Chyi Wang ,  Chih-Hsien Lin ,  Chun-Hon Chen ,  Tien-I Bao ,  Syun-Ming Jang

IPC分类号： H01L2120

CPC分类号： H01L28/55 ,  Y10S438/945

摘要： Within a method for fabricating a microelectronic fabrication, and the microelectronic fabrication fabricated employing the method, there is formed within the microelectronic fabrication a capacitor structure which comprises a first capacitor plate layer having formed thereupon a capacitor dielectric layer in turn having formed thereupon a second capacitor plate layer, wherein each of the foregoing layers having an exposed sidewall to thus form a series of exposed sidewalls. The capacitor structure also comprises a silicon oxide dielectric layer formed passivating the series of exposed sidewalls of the first capacitor plate layer, the capacitor dielectric layer and the second capacitor plate layer a silicon oxide dielectric layer.

摘要翻译： 在制造微电子制造的方法和使用该方法制造的微电子制造中，在微电子制造中形成电容器结构，该电容器结构包括依次形成有电容器电介质层的第一电容器板层，其上形成有第二电容器 板层，其中每个前述层具有暴露的侧壁，从而形成一系列暴露的侧壁。 电容器结构还包括形成钝化第一电容器板层的一系列暴露的侧壁，电容器介电层和第二电容器板层的氧化硅介电层的氧化硅介电层。

公开(公告)号：US06667217B1

公开(公告)日：2003-12-23

申请号：US09795115

申请日：2001-03-01

申请人： Heng-Ming Hsu ,  Jau-Yuann Chung ,  Yen-Shih Ho ,  Chun-Hon Chen ,  Kuo-Reay Peng ,  Ta-Hsun Yeh ,  Kong-Beng Thei ,  Ssu-Pin Ma

发明人： Heng-Ming Hsu ,  Jau-Yuann Chung ,  Yen-Shih Ho ,  Chun-Hon Chen ,  Kuo-Reay Peng ,  Ta-Hsun Yeh ,  Kong-Beng Thei ,  Ssu-Pin Ma

IPC分类号： H01L2120

CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01F41/042 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A process for integrating the fabrication of a thick, copper inductor structure, with the fabrication of narrow channel length CMOS devices, has been developed. The integrated process features the use of only one additional photolithographic masking step, used to form the opening in an IMD layer, that will accommodate the subsequent inductor structure. After forming damascene type openings in the same IMD layer, in the CMOS region, copper is deposited and then defined, to result in a thick, copper inductor structure, in the opening in the IMD layer, in a first region of a semiconductor substrate, as well as to result in copper interconnect structures, in the damascene type openings located in a second region of the semiconductor structure, used for the narrow channel length CMOS devices. The use of a thick, copper inductor structure, equal to the thickness of the IMD layer, results in increased inductance, or an increased quality factor, when compared to counterparts formed with thinner metal inductors.

摘要翻译： 已经开发了将厚铜电感器结构的制造与窄沟道长度CMOS器件的制造相结合的工艺。 集成过程的特征在于仅使用一个额外的光刻掩模步骤，用于在IMD层中形成开口，其将适应随后的电感器结构。 在相同的IMD层中形成镶嵌型开口之后，在CMOS区域中，沉积铜，然后限定铜，以在半导体衬底的第一区域中的IMD层的开口中产生厚的铜电感器结构， 以及在半导体结构的第二区域中的镶嵌型开口中产生用于窄沟道长度CMOS器件的铜互连结构。 与使用较薄的金属电感器形成的对应物相比，使用等于IMD层的厚度的厚铜电感器结构导致增加的电感或增加的品质因数。

公开(公告)号：US6051475A

公开(公告)日：2000-04-18

申请号：US089558

申请日：1998-06-03

申请人： Yen-Shih Ho ,  Chun-Hon Chen

发明人： Yen-Shih Ho ,  Chun-Hon Chen

IPC分类号： H01L21/02 ,  H01L21/28

CPC分类号： H01L28/40 ,  H01L28/60

摘要： A process is described for the manufacture of a capacitor having low V.sub.cc. Said process is fully compatible with standard IC manufacturing and introduces minimum modification thereto. The process involves the formation of a capacitor having both upper and lower electrodes that comprise layers of a metal silicide. The lower electrode is formed as a byproduct of the SALICIDE process while the upper electrode is formed by first laying down a layer of polysilicon followed by a layer of a silicide-forming metal such as titanium, cobalt, or tungsten. Sufficient of the metal must be provided to ensure that all of the polysilicon gets transformed to silicide.

摘要翻译： 描述了制造具有低Vcc的电容器的工艺。 所述方法与标准IC制造完全兼容，并对其进行最小修改。 该方法包括形成具有包括金属硅化物层的上电极和下电极的电容器。 下电极形成为SALICIDE工艺的副产物，而上电极通过首先铺设多晶硅层，然后形成诸如钛，钴或钨的硅化物形成金属层而形成。 必须提供足够的金属以确保所有的多晶硅转变为硅化物。

公开(公告)号：US20050206469A1

公开(公告)日：2005-09-22

申请号：US10804899

申请日：2004-03-19

申请人： Wen-Chin Lin ,  Denny Tang ,  Li-Shyue Lai ,  Chung-Long Chang ,  Chun-Hon Chen

发明人： Wen-Chin Lin ,  Denny Tang ,  Li-Shyue Lai ,  Chung-Long Chang ,  Chun-Hon Chen

IPC分类号： H01L23/522 ,  H01P1/36

CPC分类号： H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A capacitor for use within a microelectronic product employs a first capacitor plate layer that includes a first series of horizontally separated and interconnected tines. A capacitor dielectric layer separates the first capacitor plate layer from a second capacitor plate layer. The second capacitor plate layer includes a second series of horizontally separated and interconnected tines horizontally interdigitated with the first series of horizontally separated and interconnected tines. The capacitor is formed employing a self-aligned method and the capacitor dielectric layer is formed in a serpentine shape.

摘要翻译： 在微电子产品中使用的电容器采用第一电容器板层，其包括第一系列水平分离和互连的尖齿。 电容器电介质层将第一电容器板层与第二电容器板层分开。 第二电容器板层包括与第一系列水平分离和互相联接的齿水平地交叉指向的第二系列水平分离和互连的齿。 使用自对准方法形成电容器，并且电容器介电层形成为蛇形形状。

公开(公告)号：US20050077581A1

公开(公告)日：2005-04-14

申请号：US10683900

申请日：2003-10-10

申请人： Chung-Long Chang ,  Chun-Hon Chen

发明人： Chung-Long Chang ,  Chun-Hon Chen

IPC分类号： H01L23/522 ,  H01L29/76

CPC分类号： H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal-over-metal (MOM) device and the method for manufacturing same is provided. The device has at least one device cell on a first layer comprising a frame piece and a center piece surrounded by the frame piece. The center piece has a cross-shape center portion defining four quadrants of space between the frame and center pieces. The center piece has one or more center fingers each extending from at least one of the four ends thereof within a quadrant. The frame piece also has one or more frame fingers extending therefrom, each being in at least one quadrant and not being overlapped with the center finger in the same quadrant.

公开(公告)号：US06583491B1

公开(公告)日：2003-06-24

申请号：US10143162

申请日：2002-05-09

申请人： Chi-Feng Huang ,  Chun-Hon Chen

发明人： Chi-Feng Huang ,  Chun-Hon Chen

IPC分类号： H01L2900

CPC分类号： H01L28/55

摘要： Within a method for fabricating a microelectronic fabrication, and the microelectronic fabrication fabricated employing the method, there is formed within the microelectronic fabrication a capacitor structure upon a conductor stud layer formed into a first via defined by a patterned dielectric layer to reach a one of a pair of patterned conductor layers within the microelectronic fabrication prior to forming through the patterned dielectric layer a second via to reach the other of the pair of patterned conductor layers within the microelectronic fabrication. The method provides the resulting microelectronic fabrication with enhanced reliability and performance.

摘要翻译： 在制造微电子制造的方法和使用该方法制造的微电子制造中，在微电子制造中形成电容器结构，该电容器结构形成在由图案化的介电层限定的第一通孔中的导体柱层上，以达到 在微电子制造之前，在通过图案化的电介质层形成第二通孔以达到微电子制造中的一对图案化导体层中的另一个之前，微电子制造中的一对图案化导体层。 该方法提供了所得的微电子制造，具有增强的可靠性和性能。

公开(公告)号：US07317221B2

公开(公告)日：2008-01-08

申请号：US10729034

申请日：2003-12-04

申请人： Kuan-Lun Chang ,  Chuan-Ying Lee ,  Chun-Hon Chen

发明人： Kuan-Lun Chang ,  Chuan-Ying Lee ,  Chun-Hon Chen

IPC分类号： H01L29/72

CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S438/957 ,  H01L2924/00

摘要： A stacked integrated circuit (IC) MIM capacitor structure and method for forming the same the MIM capacitor structure including a first MIM capacitor structure formed in a first IMD layer comprising an first upper and first lower electrode portions; at least a second MIM capacitor structure arranged in stacked relationship in an overlying IMD layer comprising a second upper electrode and second lower electrode to form an MIM capacitor stack; wherein, the first lower electrode is arranged in common electrical signal communication comprising metal filled vias with the second upper electrode and the first upper electrode is arranged in common electrical signal communication with the second lower electrode.

摘要翻译： 一种用于形成MIM电容器结构的叠层集成电路（IC）MIM电容器结构及方法，包括形成在包括第一上电极部分和第一下电极部分的第一IMD层中的第一MIM电容器结构; 至少第二MIM电容器结构，以层叠的关系布置在包括第二上电极和第二下电极的上覆IMD层中，以形成MIM电容器堆叠; 其中，所述第一下部电极布置成共同的电信号通信，包括金属填充的通孔与所述第二上部电极和所述第一上部电极被布置成与所述第二下部电极共同的电信号通信。

公开(公告)号：US07294544B1

公开(公告)日：2007-11-13

申请号：US09249254

申请日：1999-02-12

申请人： Yen-Shih Ho ,  Jau-Yuann Chung ,  Chun-Hon Chen ,  Hun-Jan Tao

发明人： Yen-Shih Ho ,  Jau-Yuann Chung ,  Chun-Hon Chen ,  Hun-Jan Tao

IPC分类号： H01L21/336

CPC分类号： H01L21/8221 ,  H01L23/5223 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating an improved metal-insulator-metal capacitor is achieved. An insulating layer is provided overlying conducting lines on a semiconductor substrate. Via openings through the insulating layer to the conducting lines are filled with metal plugs. A first metal layer is deposited overlying the insulating layer and the metal plugs. A capacitor dielectric layer is deposited overlying the first metal layer wherein capacitor dielectric layer is deposited as a dual layer, each layer deposited within a separate chamber whereby pinholes are eliminated. A second metal layer and a barrier metal layer are deposited overlying the capacitor dielectric layer. The second metal layer and the barrier metal layer are patterned to form a top plate electrode. Thereafter, the capacitor dielectric layer and the first metal layer are patterned to form a bottom plate electrode completing fabrication of a metal-insulator-metal capacitor.

摘要翻译： 实现了一种制造改进的金属 - 绝缘体 - 金属电容器的方法。 在半导体衬底上覆盖导电线的绝缘层。 通过绝缘层到导线的开口填充有金属插头。 沉积在绝缘层和金属插头上的第一金属层。 电容器电介质层沉积在第一金属层上，其中电容器电介质层被沉积为双层，每层沉积在单独的室内，由此消除针孔。 沉积在电容器介电层上的第二金属层和阻挡金属层。 将第二金属层和阻挡金属层图案化以形成顶板电极。 此后，对电容器电介质层和第一金属层进行图案化以形成完成金属 - 绝缘体 - 金属电容器的制造的底板电极。

公开(公告)号：US06949781B2

公开(公告)日：2005-09-27

申请号：US10683900

申请日：2003-10-10

申请人： Chung-Long Chang ,  Chun-Hon Chen

发明人： Chung-Long Chang ,  Chun-Hon Chen

IPC分类号： H01L23/522 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal-over-metal (MOM) device and the method for manufacturing same is provided. The device has at least one device cell on a first layer comprising a frame piece and a center piece surrounded by the frame piece. The center piece has a cross-shape center portion defining four quadrants of space between the frame and center pieces. The center piece has one or more center fingers each extending from at least one of the four ends thereof within a quadrant. The frame piece also has one or more frame fingers extending therefrom, each being in at least one quadrant and not being overlapped with the center finger in the same quadrant.

摘要翻译： 提供金属金属（MOM）器件及其制造方法。 该设备在第一层上具有至少一个设备单元，该设备单元包括框架件和被框架件包围的中心件。 中心件具有在框架和中心件之间限定四个空间象限的十字形中心部分。 中心件具有一个或多个中心指，每个中指在其四分之一的四个端部中的至少一个上延伸。 框架件还具有从其延伸的一个或多个框架指状物，每个框架指状物在至少一个象限中，并且不与中心手指重叠在同一象限中。