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    Semiconductor integrated circuit device
    1.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US5512766A

    公开(公告)日：1996-04-30

    申请号：US137958

    申请日：1993-10-15

    申请人： Mitsugu Kusunoki ,  Shuuichi Miyaoka ,  Michiaki Nakayama ,  Kouji Kobayashi ,  Masato Ikeda ,  Takashi Ogata

    发明人： Mitsugu Kusunoki ,  Shuuichi Miyaoka ,  Michiaki Nakayama ,  Kouji Kobayashi ,  Masato Ikeda ,  Takashi Ogata

    IPC分类号： G11C11/412 ,  G11C5/02 ,  G11C11/40 ,  G11C11/401 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/118 ,  H03K19/0175 ,  H03K19/177 ,  H01L27/02 ,  H01L27/10

    CPC分类号： G11C5/025 ,  H03K19/017527 ,  H03K19/17704 ,  Y10S257/906

    摘要： A logic block of a memory (LSI) with logic functions includes RAM macrocells (RAMO-RAM7) and a centrally located gate array (GAO-GA5). Clock pulse shaping circuits (CSPO, CSP1) and input/output portion (I/O) surround the logic block. The logic block power supply includes a smoothing capacitor (CC) that is substantially the same size as a cell (GC) of the gate array. Each RAM macrocell has memory mats (MATOO-MAT21), word lines (WO-W127), data lines (DO-D7), and peripheral circuits (MPCOO-MPC21), which includes an address decoder and a sense amp (SAO). An input unit cell (ICO) receives ECL level signals and outputs ECL level signals (FIG. 5 ) and MOS level signals (FIG. 6 ). The input unit cells and analogous output unit cells (OCO) are selectively used singly or in parallel to accommodate signals of different form and driving capability. A wiring line replacement region (LRP) connects memory macrocell wiring lines with logic block wiring lines. A sequence control circuit cell or aligner (ALNO, ALN1) contiguous to the RAM macrocells transmits output signals to the logic block on the wiring lines. A clock signal distribution circuit (CDA) is arranged centrally of the RAM macrocells for distributing ECL level clock signals. The clock signal distribution circuit includes clock switch amplifier circuits (CSAO-CSA9) including bipolar transistors and MOSFETs (FIG. 23 ).

    摘要翻译： 具有逻辑功能的存储器（LSI）的逻辑块包括RAM宏单元（RAMO-RAM7）和位于中心的门阵列（GAO-GA5）。 时钟脉冲整形电路（CSPO，CSP1）和输入/输出部分（I / O）围绕逻辑块。 逻辑块电源包括与门阵列的单元（GC）基本相同的尺寸的平滑电容器（CC）。 每个RAM宏单元具有包括地址解码器和读出放大器（SAO）的存储器垫（MATOO-MAT21），字线（WO-W127），数据线（_DO-_D7）和外围电路（MPCOO-MPC21）。 输入单元单元（ICO）接收ECL电平信号并输出​​ECL电平信号（图5）和MOS电平信号（图6）。 输入单元单元和类似输出单元单元（OCO）可以单独或并行选择性地使用，以适应不同形式和驱动能力的信号。 布线更换区域（LRP）将存储器宏单元布线与逻辑块布线相连。 与RAM宏单元相邻的序列控制电路单元或对准器（ALNO，ALN1）将输出信号发送到布线上的逻辑块。 时钟信号分配电路（CDA）被布置在RAM宏单元的中央以分配ECL电平时钟信号。 时钟信号分配电路包括包括双极晶体管和MOSFET的时钟转换放大器电路（CSAO-CSA9）（图23）。

    Semiconductor integrated circuit device having stabilizing capacitors connected between power lines of main amplifiers
    4.
    发明授权
    Semiconductor integrated circuit device having stabilizing capacitors connected between power lines of main amplifiers 有权
    半导体集成电路器件具有连接在主放大器的电源线之间的稳定电容器

    公开(公告)号：US06191990B1

    公开(公告)日：2001-02-20

    申请号：US09507785

    申请日：2000-02-22

    申请人： Nobutaka Itoh ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Michiaki Nakayama ,  Mitsugu Kusunoki ,  Kazumasa Takashima ,  Hideki Sakakibara ,  Toru Kobayashi

    发明人： Nobutaka Itoh ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Michiaki Nakayama ,  Mitsugu Kusunoki ,  Kazumasa Takashima ,  Hideki Sakakibara ,  Toru Kobayashi

    IPC分类号： G11C702

    CPC分类号： G11C7/18 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10897 ,  H01L27/11 ,  H01L28/75

    摘要： A semiconductor integrated circuit device has a memory array which includes amplifying MOSFETs of sense amplifiers which amplify small voltages read out of dynamic memory cells onto bit lines and column switch MOSFETs which select bit lines, a read/write section which includes main amplifiers for reading out stored data from memory cells selected by the column switch, and a logic circuit which implements the input/output operation of data with the read/write section. Two capacitors each having a first electrode which corresponds to a plate electrode with the same structure as that of storage capacitors of dynamic memory cells and a second electrode which is multiple commonly-connected storage nodes of the storage capacitors are arranged in serial connection, disposed contiguously to the read/write section, and connected between operation voltage lines of the read/write section.

    摘要翻译： 一种半导体集成电路器件具有存储器阵列，该存储器阵列包括将读出放大器中的动态存储单元读出的小电压放大到位线和选择位线的列开关MOSFET的读出放大器的MOSFET，包括用于读出的主放大器的读/写部分 来自由列开关选择的存储器单元的存储数据，以及实现与读/写部分的数据的输入/输出操作的逻辑电路。 两个电容器具有第一电极，其对应于具有与动态存储单元的存储电容器相同结构的平板电极的第一电极和作为存储电容器的多个共同连接的存储节点的第二电极串联连接设置 到读/写部分，并连接在读/写部分的操作电压线之间。

    Semiconductor integrated circuit device
    5.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US07078928B2

    公开(公告)日：2006-07-18

    申请号：US10736673

    申请日：2003-12-17

    申请人： Ryusuke Sahara ,  Kozaburo Kurita ,  Yuuji Suzuki ,  Mitsugu Kusunoki ,  Hideki Sakakibara

    发明人： Ryusuke Sahara ,  Kozaburo Kurita ,  Yuuji Suzuki ,  Mitsugu Kusunoki ,  Hideki Sakakibara

    IPC分类号： H03K19/00 ,  G01R31/28 ,  H03H11/26

    CPC分类号： G01R31/318577

    摘要： The present invention provides a semiconductor integrated circuit device equipped with at least one pulse generator which generates a pulse of a pulse with shorter than a rising time up to the full amplitude of a transfer signal.A first signal and a second signal supplied from outside through a first signal path and a second signal path are respectively transferred to the pulse generator. When a rising time up to the full amplitude at any one of buffers in the first signal path and the second signal path is longer than a pulse width of a pulse to be formed by the pulse generator, the difference in phase between the first signal and the second signal is caused to correspond to a pulse width of a first pulse.

    摘要翻译： 本发明提供一种配备有至少一个脉冲发生器的半导体集成电路器件，该脉冲发生器产生的脉冲脉冲短于传输信号的全幅度的上升时间。 通过第一信号路径和第二信号路径从外部提供的第一信号和第二信号分别传送到脉冲发生器。 当在第一信号路径和第二信号路径中的任何一个缓冲器上的上升时间达到全幅度时，脉冲发生器将形成的脉冲的脉冲宽度大于第一信号与第二信号路径之间的相位差 使第二信号对应于第一脉冲的脉冲宽度。

    Semiconductor device
    7.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US07903013B2

    公开(公告)日：2011-03-08

    申请号：US12507660

    申请日：2009-07-22

    申请人： Kenichiro Yamaguchi ,  Atsushi Okumura ,  Mitsugu Kusunoki ,  Tomoo Murata

    发明人： Kenichiro Yamaguchi ,  Atsushi Okumura ,  Mitsugu Kusunoki ,  Tomoo Murata

    IPC分类号： H03M1/66

    CPC分类号： H03M1/0643 ,  H01L27/0203 ,  H03M1/687 ,  H03M1/745 ,  H03M1/785 ,  Y10T307/696

    摘要： Operating speed as well as output accuracy of a D-A converter is enhanced. With a semiconductor device including unit current sources, and unit current source switches, plural current source elements constituting each of the unit current sources are disposed so as to be evenly dispersed, thereby reducing errors of the current source element, dependent on distance while the unit current source switches are concentratedly disposed in a small region, thereby mitigating delay in operation, attributable to parasitic capacitance. In addition, with the semiconductor device including R2R resistance ladders, the R2R resistance ladder is provided on the positive and the negative of each of the unit current source switches, and the respective R2R resistance ladders are shorted with each other at respective nodes on a unit current source switch-by-unit current source switch basis, are rendered identical in length, thereby cancelling out a nonlinearity error attributable to wiring parasitic resistance.

    摘要翻译： 提高了D-A转换器的工作速度和输出精度。 利用包括单位电流源和单位电流源开关的半导体器件，构成每个单位电流源的多个电流源元件被布置成均匀分散，从而根据距离减小电流源元件的误差，而单元 电流源开关集中地设置在较小的区域中，从而减轻了由寄生电容引起的工作延迟。 另外，对于包含R2R电阻梯的半导体装置，在每个单位电流源开关的正极和负极上设置R2R电阻梯，并且相应的R2R电阻梯在单元的相应节点处相互短路 电流源逐个电流源开关基础的长度相同，从而消除归因于布线寄生电阻的非线性误差。

    Semiconductor device
    8.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20060245266A1

    公开(公告)日：2006-11-02

    申请号：US11409963

    申请日：2006-04-25

    申请人： Ryusuke Sahara ,  Mitsugu Kusunoki ,  Kazutaka Mori ,  Hiroshige Kogayu

    发明人： Ryusuke Sahara ,  Mitsugu Kusunoki ,  Kazutaka Mori ,  Hiroshige Kogayu

    IPC分类号： G11C7/10

    CPC分类号： H03M1/1061 ,  H03M1/687 ,  H03M1/785 ,  H03M1/808

    摘要： A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.

    摘要翻译： 具有包括多个第一存储单元的存储器垫的DAC和连接到多个第一存储单元的多个输出线。 多个存储单元中的每一个具有包括双极晶体管的第一存储器部分，并且基于双极晶体管的结是否被破坏来存储非易失性的信息，以及连接到第一存储器部分并用于输出的第二存储器部分 信息到多个输出行中的相应一个。 DAC具有第一模式，其中当信息被写入第二存储器部分时，信息从第一存储器部分传送到第二存储器部分，以及第二模式，其中第二存储器部分被外部指定并且信息被写入 第二存储器部分。 因此，可以提高D / A转换器的性能。

    Semiconductor integrated circuit device
    10.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US06806743B2

    公开(公告)日：2004-10-19

    申请号：US10360868

    申请日：2003-02-10

    申请人： Kayoko Saito ,  Mitsugu Kusunoki

    发明人： Kayoko Saito ,  Mitsugu Kusunoki

    IPC分类号： H03F345

    CPC分类号： H03F3/45219 ,  H03F3/72 ,  H03F2203/45396 ,  H03F2203/45506

    摘要： The present invention provides a semiconductor integrated circuit device equipped with an input circuit capable of stably performing a high-speed operation up to a low voltage. A rail to rail circuit constitutes a differential input circuit, and a circuit similar to such a differential input circuit is used to constitute a bias circuit. A pair of output terminals of a differential circuit constituting such a bias circuit is commonly connected to form a bias voltage corresponding to a middle point. The bias voltage is supplied to the gates of current source MOSFET and the gates of cascode-connected MOSFETs in the differential input circuit, and the gates of the corresponding current source MOSFETs and cascode-connected MOSFETs in the bias circuit corresponding to itself.

    摘要翻译： 本发明提供一种配备有能够稳定地进行低电压的高速运转的输入电路的半导体集成电路装置。 轨到轨电路构成差分输入电路，并且使用类似于这种差分输入电路的电路来构成偏置电路。 构成这种偏置电路的差分电路的一对输出端子通常连接以形成对应于中点的偏置电压。 偏置电压被提供给电流源MOSFET的栅极和差分输入电路中的共源共栅MOSFET的栅极，偏置电路中对应的电流源MOSFET和共源共栅MOSFET的栅极对应于其自身。