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    EMBEDDED RESILIENT BUFFER
    2.
    发明申请
    EMBEDDED RESILIENT BUFFER 有权
    嵌入式电阻缓冲器

    公开(公告)号：US20140317458A1

    公开(公告)日：2014-10-23

    申请号：US13867968

    申请日：2013-04-22

    Applicant: Somnath Paul ,  Sriram R. Vangal

    Inventor： Somnath Paul ,  Sriram R. Vangal

    IPC: G06F11/07

    CPC classification number: G06F11/0787 ,  G06F5/065 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/1407 ,  G06F11/1645 ,  G06F11/26 ,  G06F13/1673 ,  G06F13/1689 ,  G06F2205/067 ,  G11C29/003 ,  G11C29/023 ,  G11C29/028 ,  H03K19/00 ,  H04L1/00 ,  H04L2012/5681 ,  Y02D10/14

    Abstract: Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input, the first sequential for double sampling the first input; a compare unit to receive an output from the first sequential unit; and a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit.

    Abstract translation: 描述了一种装置，包括：第一顺序单元; 与第一顺序单元并联耦合的第一队列，使得第一队列和第一顺序单元接收第一输入，用于对第一输入进行双倍采样的第一序列; 比较单元，用于接收来自第一顺序单元的输出; 以及由前一周期的写指针控制的第一选择单元，所述第一选择单元接收所述第一队列的每个存储单元的输出，其中所述第一选择单元生成用于由所述第一比较单元进行比较的输出。

    EMBEDDED RESILIENT BUFFER
    3.
    发明申请
    EMBEDDED RESILIENT BUFFER 审中-公开
    嵌入式电阻缓冲器

    公开(公告)号：US20160232051A1

    公开(公告)日：2016-08-11

    申请号：US15132027

    申请日：2016-04-18

    Applicant: Somnath Paul ,  Sriram R. Vangal

    Inventor： Somnath Paul ,  Sriram R. Vangal

    IPC: G06F11/07 ,  G06F13/16 ,  G06F5/06 ,  G06F11/16

    CPC classification number: G06F11/0787 ,  G06F5/065 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/1407 ,  G06F11/1645 ,  G06F11/26 ,  G06F13/1673 ,  G06F13/1689 ,  G06F2205/067 ,  G11C29/003 ,  G11C29/023 ,  G11C29/028 ,  H03K19/00 ,  H04L1/00 ,  H04L2012/5681 ,  Y02D10/14

    Abstract: Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input, the first sequential for double sampling the first input; a compare unit to receive an output from the first sequential unit; and a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit.

    Abstract translation: 描述了一种装置，包括：第一顺序单元; 与第一顺序单元并联耦合的第一队列，使得第一队列和第一顺序单元接收第一输入，用于对第一输入进行双倍采样的第一序列; 比较单元，用于接收来自第一顺序单元的输出; 以及由前一周期的写指针控制的第一选择单元，所述第一选择单元接收所述第一队列的每个存储单元的输出，其中所述第一选择单元生成用于由所述第一比较单元进行比较的输出。

    Techniques for Resilient Communication
    4.
    发明申请
    Techniques for Resilient Communication 有权
    弹性通信技术

    公开(公告)号：US20140095953A1

    公开(公告)日：2014-04-03

    申请号：US13631937

    申请日：2012-09-29

    Applicant: Somnath Paul ,  Sriram R. Vangal ,  Michael D. Abbott ,  Eugene M. Kishinevsky

    Inventor： Somnath Paul ,  Sriram R. Vangal ,  Michael D. Abbott ,  Eugene M. Kishinevsky

    IPC: G06F11/14

    CPC classification number: G06F11/1443 ,  H04L1/20 ,  H04L1/242

    Abstract: Techniques for resilient communication. A data path stores data to be transmitted over a link to a receiving node. An output stage is coupled between the data path and the link. The output stage includes double sampling mechanisms to preserve a copy of data transmitted over the link to the receiving node. Error detection circuitry is coupled with the output stage to detect transient timing errors in the data path or output stage. The error detection circuitry causes the output stage to send the copy of the data transmitted over the link in response to detecting an error.

    Abstract translation: 弹性沟通技巧。 数据路径存储要通过链接发送到接收节点的数据。 输出级耦合在数据路径和链路之间。 输出级包括双重采样机制，以保留通过链路传送到接收节点的数据副本。 错误检测电路与输出级耦合以检测数据通路或输出级中的瞬态定时误差。 响应于检测到错误，错误检测电路使得​​输出级发送通过链路发送的数据的副本。

    Using criticality information to route cache coherency communications
    5.
    发明申请
    Using criticality information to route cache coherency communications 有权
    使用关键性信息来路由缓存一致性通信

    公开(公告)号：US20090300292A1

    公开(公告)日：2009-12-03

    申请号：US12156343

    申请日：2008-05-30

    Applicant: Zhen Fang ,  Liqun Cheng ,  Sriram R. Vangal

    Inventor： Zhen Fang ,  Liqun Cheng ,  Sriram R. Vangal

    IPC: G06F12/00

    CPC classification number: G06F12/0822

    Abstract: In one embodiment, the present invention includes a method for receiving a cache coherency message in an interconnect router from a caching agent, mapping the message to a criticality level according to a predetermined mapping, and appending the criticality level to each flow control unit of the message, which can be transmitted from the interconnect router based at least in part on the criticality level. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括一种用于从高速缓存代理器接收互连路由器中的高速缓存一致性消息的方法，用于根据预定映射将消息映射到临界级，并将关键性级别附加到每个流控制单元 消息，其可以至少部分地基于关键性级别从互连路由器发送。 描述和要求保护其他实施例。

    Floating point multiply accumulator
    7.
    发明授权
    Floating point multiply accumulator 失效

    公开(公告)号：US07080111B2

    公开(公告)日：2006-07-18

    申请号：US09873557

    申请日：2001-06-04

    Applicant: Amaresh Pangal ,  Dinesh Somasekhar ,  Shekhar Y. Borkar ,  Sriram R. Vangal

    Inventor： Amaresh Pangal ,  Dinesh Somasekhar ,  Shekhar Y. Borkar ,  Sriram R. Vangal

    IPC: G06F7/38

    CPC classification number: G06F7/5443 ,  G06F7/483 ,  G06F7/49936

    Abstract: A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accumulation. An adder circuit accumulates the converted products in carry-save format. Because the products being summed are in carry-save format, post-normalization is avoided within the adder feedback loop. The adder operates on floating point number representations having exponents with a least significant bit weight of thirty-two, and exponent comparisons within the adder exponent path are limited in size. Variable shifters are avoided in the adder mantissa path. A single mantissa shift of thirty-two bits is provided by a conditional shifter.

    Method and apparatus for driving data packets
    9.
    发明授权
    Method and apparatus for driving data packets 失效

    公开(公告)号：US06853644B1

    公开(公告)日：2005-02-08

    申请号：US09470080

    申请日：1999-12-22

    Applicant: Sriram R. Vangal ,  Howard A. Wilson

    Inventor： Sriram R. Vangal ,  Howard A. Wilson

    IPC: H04L12/28 ,  H04L12/56

    CPC classification number: H04L45/00 ,  H04L12/10 ,  H04L45/12 ,  H04L45/60

    Abstract: An apparatus for driver power and size selection includes in one embodiment a controller for controlling the enabling and disabling of legs in a legged driver, the legged driver providing only that amount of power necessary to transfer a data packet from its current location to its destination location. A method of forwarding data packets includes determining the distance between a current location of a data packet and the destination location of the data packet, and enabling as many legs of a legged driver as are necessary to power the transfer of the data packet to its destination.

    Flip flop circuit
    10.
    发明授权
    Flip flop circuit 失效
    触发电路

    公开(公告)号：US06459316B1

    公开(公告)日：2002-10-01

    申请号：US09733216

    申请日：2000-12-08

    Applicant: Sriram R. Vangal ,  Dinesh Somasekhar

    Inventor： Sriram R. Vangal ,  Dinesh Somasekhar

    IPC: H03K3289

    CPC classification number: H03K3/0372 ,  H03K3/356121

    Abstract: A dual rail flip flop with complementary outputs includes a master stage with embedded logic, a sensing stage, and one or more slave stages. The flip flop operates in a pre-charge state and an evaluate state. During the pre-charge state when a clock signal is low, the flip flop pre-charges internal keeper nodes to a high value. When the clock signal transitions high, the flip flop enters an evaluation state and one of the internal keeper nodes evaluates to a low value. The sense stage senses which of the internal keeper nodes is evaluating to zero, and drives it to zero faster. The slave stages reflect the state of the internal keeper nodes during the evaluate state, and maintain their states during the pre-charge state.

    Abstract translation: 具有互补输出的双轨触发器包括具有嵌入式逻辑的主级，感测级和一个或多个从动级。 触发器工作在预充电状态和评估状态。 在时钟信号为低电平的预充电状态期间，触发器将内部保持器节点预充电到高电平。 当时钟信号变为高电平时，触发器进入评估状态，并且内部保持器节点之一评估为低值。 感觉阶段感知内部维护者节点评估为零，并将其驱动到零更快。 从站阶段在评估状态期间反映内部守门员节点的状态，并在预充电状态期间维持其状态。

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