公开(公告)号：US06514843B2

公开(公告)日：2003-02-04

申请号：US09844977

申请日：2001-04-27

申请人： Omer Dokumaci ,  Oleg Gluschenkov ,  Suryanarayan G. Hegde ,  Richard Kaplan ,  Mukesh Khare

发明人： Omer Dokumaci ,  Oleg Gluschenkov ,  Suryanarayan G. Hegde ,  Richard Kaplan ,  Mukesh Khare

IPC分类号： H01L214763

CPC分类号： H01L21/28176 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28247 ,  H01L29/42368 ,  H01L29/4941

摘要： A method of enhancing the rate of transistor gate corner oxidation, without significantly increasing the thermal budget of the overall processing scheme is provided. Specifically, the method of the present invention includes implanting ions into gate corners of a Si-containing transistor, and exposing the transistor including implanted transistor gate corners to an oxidizing ambient. The ions employed in the implant step include Si; non-retarding oxidation ions such as O, Ge, As, B, P, In, Sb, Ga, F, Cl, He, Ar, Kr, and Xe; and mixtures thereof.

公开(公告)号：US06727142B1

公开(公告)日：2004-04-27

申请号：US10284508

申请日：2002-10-29

申请人： Oleg Gluschenkov ,  Suryanarayan G. Hegde ,  Helmut H. Tews

发明人： Oleg Gluschenkov ,  Suryanarayan G. Hegde ,  Helmut H. Tews

IPC分类号： H01L2126

CPC分类号： H01L21/02332 ,  H01L21/02247 ,  H01L21/3141 ,  H01L21/3144 ,  H01L21/32105

摘要： Forming a vertical MOS transistor or making another three-dimensional integrated circuit structure in a silicon wafer exposes planes having at least two different crystallographic orientations. Growing oxide on different crystal planes is inherently at different growth rates because the inter-atomic spacing is different in the different planes. Heating the silicon in a nitrogen-containing ambient to form a thin layer of nitride and then growing the oxide through the thin nitrided layer reduces the difference in oxide thickness to less than 1%.

摘要翻译： 形成垂直MOS晶体管或在硅晶片中制造另一三维集成电路结构暴露具有至少两个不同晶体取向的平面。 不同晶面上生长的氧化物固有地在不同的生长速率下，因为不同平面中原子间的间距是不同的。 在含氮环境中加热硅以形成氮化物薄层，然后通过薄氮化层生长氧化物，将氧化物厚度的差异减小到小于1％。

公开(公告)号：US06329704B1

公开(公告)日：2001-12-11

申请号：US09458530

申请日：1999-12-09

申请人： Hiroyuki Akatsu ,  Omer H. Dokumaci ,  Suryanarayan G. Hegde ,  Yujun Li ,  Rajesh Rengarajan ,  Paul A. Ronsheim

发明人： Hiroyuki Akatsu ,  Omer H. Dokumaci ,  Suryanarayan G. Hegde ,  Yujun Li ,  Rajesh Rengarajan ,  Paul A. Ronsheim

IPC分类号： H01L29167

CPC分类号： H01L21/2652 ,  H01L21/2254 ,  H01L21/2255 ,  H01L29/6659

摘要： A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate. A low thermal budget is maintained because of the proximity of the as-implanted peak concentration to the interface and the presence of species implanted through the dielectric film and into the substrate.

摘要翻译： 一种用于在硅衬底内形成超浅结深度掺杂区的工艺。 该方法包括在衬底上形成电介质膜，然后将离子掺杂剂物质注入结构中。 植入物种的轮廓包括通过电介质膜注入硅衬底中的群体，以及刻意限制在电介质膜中的接近于介电膜和硅衬底之间界面的峰值浓度。 使用高能量，低剂量的植入工艺，并且产生基本上不含位错环和其它缺陷簇的结构。 使用退火工艺来驱动更接近界面的峰值浓度，以及从电介质膜到硅衬底的最初注入物质的一些群体。 由于植入的峰浓度与界面的接近以及通过电介质膜注入并进入衬底的物质的存在，维持了低热量预算。

公开(公告)号：US4931887A

公开(公告)日：1990-06-05

申请号：US151134

申请日：1988-02-01

申请人： Suryanarayan G. Hegde ,  Robert A. Scranton ,  Edward J. Yarmchuk

发明人： Suryanarayan G. Hegde ,  Robert A. Scranton ,  Edward J. Yarmchuk

IPC分类号： G01B7/14 ,  G11B5/10 ,  G11B5/105 ,  G11B5/48 ,  G11B5/58 ,  G11B5/60 ,  G11B21/21

CPC分类号： G11B5/6005 ,  G01B7/14 ,  G11B5/10 ,  G11B5/105 ,  G11B5/488 ,  G11B5/58

摘要： A device and method for capacitive measurement and control of the fly height of a recording slider. A recording slider is vertically spaced from a rotating disk surface by an "air bearing". The disk has a first electrically conductive pattern at its surface. The first pattern has an edge with a length extending, for example, radially. The recording slider has one or more electrically conductive rails extending transverse to the radial pattern on the rotating disk. As the disk rotates, the edge of the pattern on the disk scans across the rail of the slider. By measuring the electrical capacitance between the slider and the pattern on the disk, and by processing the electrical capacitance measurement signal, a vertical spacing signal proportional to the vertical spacing between the disk and the slider can be obtained.

公开(公告)号：US06803270B2

公开(公告)日：2004-10-12

申请号：US10248819

申请日：2003-02-21

申请人： Omer H. Dokumachi ,  Dureseti Chidambarrao ,  Suryanarayan G. Hegde

发明人： Omer H. Dokumachi ,  Dureseti Chidambarrao ,  Suryanarayan G. Hegde

IPC分类号： H01L218222

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814

摘要： The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and longitudinal compressive stress on the PFETs, by implanting in the sources and drains of the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.

摘要翻译： CMOS电路的速度通过在NFET上施加纵向拉伸应力和PFET上的纵向压缩应力，通过将来自周期表第八列的NFET离子的源和漏极注入氢并将其植入源中来改进 和来自周期表第四和第六列的PFET离子的漏极。

公开(公告)号：US06348388B1

公开(公告)日：2002-02-19

申请号：US09668638

申请日：2000-09-20

申请人： Johnathan E. Faltermeier ,  Ulrike Gruening ,  Suryanarayan G. Hegde ,  Rajarao Jammy ,  Brian S. Lee ,  Helmut H. Tews

发明人： Johnathan E. Faltermeier ,  Ulrike Gruening ,  Suryanarayan G. Hegde ,  Rajarao Jammy ,  Brian S. Lee ,  Helmut H. Tews

IPC分类号： H01L21336

CPC分类号： H01L21/28211 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L21/28238 ,  H01L27/10864 ,  H01L27/10876 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7813 ,  H01L29/7827 ,  Y10S438/931

摘要： A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a crystal plane and a crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the crystal plane of the trench side wall, but not into the crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.

摘要翻译： 一种用于制造垂直晶体管的栅极氧化物的工艺。 在第一步骤中，在衬底中形成沟槽，沟槽从衬底的顶表面延伸并且具有沟槽底部和沟槽侧壁。 沟槽侧壁包括<100>晶面和<110>晶面。 接下来，在沟槽侧壁上形成均匀厚度的牺牲层。 在形成牺牲层之后，通过牺牲层注入氮离子，使得氮离子注入沟槽侧壁的<110>晶面，而不是注入沟槽侧壁的<100>晶面。 然后去除牺牲层，并且沟槽侧壁被氧化以形成栅极氧化物。

公开(公告)号：US6150670A

公开(公告)日：2000-11-21

申请号：US450546

申请日：1999-11-30

申请人： Johnathan E. Faltermeier ,  Ulrike Gruening ,  Suryanarayan G. Hegde ,  Rajarao Jammy ,  Brian S. Lee ,  Helmut H. Tews

发明人： Johnathan E. Faltermeier ,  Ulrike Gruening ,  Suryanarayan G. Hegde ,  Rajarao Jammy ,  Brian S. Lee ,  Helmut H. Tews

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/04 ,  H01L29/12 ,  H01L29/423 ,  H01L29/78 ,  H01L27/108

CPC分类号： H01L21/28211 ,  H01L21/26586 ,  H01L21/2822 ,  H01L21/28238 ,  H01L27/10876 ,  H01L29/045 ,  H01L29/66666 ,  H01L29/7827 ,  H01L21/26506 ,  H01L27/10864 ,  H01L29/4236 ,  H01L29/7813 ,  Y10S438/931

摘要： A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a crystal plane and a crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the crystal plane of the trench side wall, but not into the crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.

公开(公告)号：US20080246090A1

公开(公告)日：2008-10-09

申请号：US12119765

申请日：2008-05-13

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  MeiKei Ieong ,  Erin Catherine Jones

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  MeiKei Ieong ,  Erin Catherine Jones

IPC分类号： H01L27/12

CPC分类号： H01L29/78648 ,  H01L21/0338 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42384

摘要： A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

摘要翻译： 提供了具有横向排列的前（上）和后门的双栅极晶体管。 双栅晶体管包括在器件层下面的背栅热氧化层; 位于背栅极氧化物层下面的背栅电极; 位于器件层上方的前门热氧化物; 前栅极热氧化物上方的前栅极电极层，并与背栅电极垂直对准; 以及设置在背栅极热氧化物层上方的与第一栅极对称的晶体管体。 背栅电极具有形成在晶体管本体下方和在背栅电极的中心部分的任一侧上的氧化物层，从而将后栅极与前栅极自对准。 晶体管还包括在所述晶体管体的相对侧上的源极和漏极。

公开(公告)号：US06387782B2

公开(公告)日：2002-05-14

申请号：US09875072

申请日：2001-06-06

申请人： Hiroyuki Akatsu ,  Omer H. Dokumaci ,  Suryanarayan G. Hegde ,  Yujun Li ,  Rajesh Rengarajan ,  Paul A. Ronsheim

发明人： Hiroyuki Akatsu ,  Omer H. Dokumaci ,  Suryanarayan G. Hegde ,  Yujun Li ,  Rajesh Rengarajan ,  Paul A. Ronsheim

IPC分类号： H01L21336

CPC分类号： H01L21/2652 ,  H01L21/2254 ,  H01L21/2255 ,  H01L29/6659

摘要： A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate. A low thermal budget is maintained because of the proximity of the as-implanted peak concentration to the interface and the presence of species implanted through the dielectric film and into the substrate.

摘要翻译： 一种用于在硅衬底内形成超浅结深度掺杂区的工艺。 该方法包括在衬底上形成电介质膜，然后将离子掺杂剂物质注入结构中。 植入物种的轮廓包括通过电介质膜注入硅衬底中的群体，以及刻意限制在电介质膜中的接近于介电膜和硅衬底之间界面的峰值浓度。 使用高能量，低剂量的植入工艺，并且产生基本上不含位错环和其它缺陷簇的结构。 使用退火工艺来驱动更接近界面的峰值浓度，以及从电介质膜到硅衬底的最初注入物质的一些群体。 由于植入的峰浓度与界面的接近以及通过电介质膜注入并进入衬底的物质的存在，维持了低热量预算。

公开(公告)号：US5392177A

公开(公告)日：1995-02-21

申请号：US248137

申请日：1994-05-24

申请人： Timothy J. Chainer ,  Emanuel I. Cooper ,  Suryanarayan G. Hegde ,  Chandrasekhar Narayan

发明人： Timothy J. Chainer ,  Emanuel I. Cooper ,  Suryanarayan G. Hegde ,  Chandrasekhar Narayan

IPC分类号： G11B23/50 ,  G11B33/14

CPC分类号： G11B23/507 ,  G11B33/1453

摘要： A sealed direct access storage device wherein a head is positioned for interaction with a storage medium in which the relative humidity is controlled by placing a predetermined amount of desiccant and a predetermined amount of water in the sealed volume of the device. At any given steady state temperature within a predetermined operating range the water vapor within the free space within the device and the water contained in the desiccant are in equilibrium and the relative humidity is controlled within acceptable limits.

摘要翻译： 一种密封的直接存取存储装置，其中头被定位成与通过将预定量的干燥剂和预定量的水放置在装置的密封体积中来控制相对湿度的存储介质相互作用。 在预定操作范围内的任何给定的稳态温度下，装置内的自由空间内的水蒸气和干燥剂中所含的水均处于平衡状态，并将相对湿度控制在可接受的限度内。