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45 条记录 (耗时 0.025 秒)

    ECL EPROM with CMOS programming
    1.
    发明授权
    ECL EPROM with CMOS programming 失效
    具有CMOS编程的ECL EPROM

    公开(公告)号：US5075885A

    公开(公告)日：1991-12-24

    申请号：US287980

    申请日：1988-12-21

    申请人： Douglas D. Smith ,  Robert A. Kertis ,  Terrance L. Bowman

    发明人： Douglas D. Smith ,  Robert A. Kertis ,  Terrance L. Bowman

    IPC分类号： G11C17/18 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/10 ,  G11C16/0441 ,  G11C16/26

    摘要： The present invention provides an ECL EPROM circuit which uses a MOS memory cell. The invention includes a technique for programming the memory cell using MOS voltage levels, and also includes circuitry for reading the memory cell at ECL voltage levels. Thus, the programming and reading paths are split to give the ease of programming and the reprogrammability of MOS EPROM devices combined with the reading speed of PROM devices using ECL voltage levels. In one embodiment, two parallel paths are provided to a memory cell to enable it to separately receive reading and writing (programming) signals. The reading path employs ECL components for reading the cell, while the writing path contains MOS components for programming and verifying the cell. The memory cell itself contains a MOS memory element, an ECL pass element, and a sense element coupling the MOS memory element to the ECL pass element. The MOS memory element is coupled to the programming (writing) path, and the ECL pass element is coupled to the read path with a bipolar output transistor.

    BICMOS positive supply voltage reference
    4.
    发明授权
    BICMOS positive supply voltage reference 失效
    BICMOS正电源电压参考

    公开(公告)号：US5149988A

    公开(公告)日：1992-09-22

    申请号：US610724

    申请日：1990-11-07

    申请人： Douglas D. Smith ,  Terrance L. Bowman

    发明人： Douglas D. Smith ,  Terrance L. Bowman

    IPC分类号： G05F3/20

    CPC分类号： G05F3/20

    摘要： The present invention provides a voltage reference level using a bipolar output transistor to provide a reference voltage on a reference output line. A control circuit is used for varying the current to the base of the output transistor in response to the load on the reference output line. In addition, the control circuit provides the reference level to the output transistor. The MOS control circuit and the bipolar output transistor are fabricated on the same chip using a BICMOS process. The voltage reference provided by the control circuit is derived from a voltage level provided by a resistor coupled between the positive voltage supply and a current source.

    摘要翻译： 本发明提供使用双极性输出晶体管在基准输出线上提供参考电压的电压参考电平。 控制电路用于响应于参考输出线上的负载改变输出晶体管的基极的电流。 此外，控制电路为输出晶体管提供参考电平。 使用BICMOS工艺在同一芯片上制造MOS控制电路和双极性输出晶体管。 由控制电路提供的电压基准是由耦合在正电压源和电流源之间的电阻提供的电压电平导出的。

    BiCMOS write-recovery circuit
    5.
    发明授权
    BiCMOS write-recovery circuit 失效
    BiCMOS写恢复电路

    公开(公告)号：US4926383A

    公开(公告)日：1990-05-15

    申请号：US151377

    申请日：1988-02-02

    申请人： Robert A. Kertis ,  Douglas D. Smith

    发明人： Robert A. Kertis ,  Douglas D. Smith

    IPC分类号： G11C11/413 ,  G11C11/419

    CPC分类号： G11C11/419

    摘要： A BiCMOS write-recovery method and circuit for recovering bit lines in a digital memory system provides approximately 1 nS recovery time and allows a 256K BiCMOS SRAM to achieve 10 nS access time. All bit lines in the memory system connected to a column not being read are held at a high potential, approximately equal to the upper power supply. During a write, one bit line is pulled low and its complementary bit line is clamped with a bipolar transistor to an intermediate potential, thereby preloading the complementary bit line. Following a write, the bit line that was pulled low is pulled up with a bipolar transistor to the intermediate voltage. Simultaneously, the bit line and the complementary bit line are shunted together, then returned to the high potential. Undesired bootstrap capacitance effects in the bipolar transistors are minimized by connecting a plurality of pull-up transistors in parallel, and by feeding the clamping transistors with low impedance drivers.

    BiCMOS voltage reference generator
    6.
    发明授权
    BiCMOS voltage reference generator 失效
    BiCMOS电压参考发生器

    公开(公告)号：US4820967A

    公开(公告)日：1989-04-11

    申请号：US151348

    申请日：1988-02-02

    申请人： Robert A. Kertis ,  Douglas D. Smith

    发明人： Robert A. Kertis ,  Douglas D. Smith

    IPC分类号： G05F3/24 ,  G05F3/30 ,  H03F1/30 ,  G05F3/16

    CPC分类号： G05F3/30

    摘要： A BiCMOS voltage reference generator circuit generates and maintains a reference voltage within 3 mV over an 80.degree. C. temperture range and over a 1 volt change in power supply level. The circuit uses feedback from the output of the reference voltage generator to the current source supplying current to the voltage reference generator. This feedback increases the effective output impedance of the current source, making the reference voltage output substantially independent of power supply variations. The circuit operates with power supply differential as low as about 3 volts, and preferably is fabricated from bipolar transistors and MOS transistors on the same chip.

    Very Small Swing High Performance Asynchronous CMOS Static Memory (Multi-Port Register File) With Power Reducing Column Multiplexing Scheme
    7.
    发明申请
    Very Small Swing High Performance Asynchronous CMOS Static Memory (Multi-Port Register File) With Power Reducing Column Multiplexing Scheme 有权
    具有减少功率的多路复用方案的非常小的摆动高性能异步CMOS静态存储器（多端口寄存器文件）

    公开(公告)号：US20100177581A1

    公开(公告)日：2010-07-15

    申请号：US12617570

    申请日：2009-11-12

    申请人： Mark Slamowitz ,  Douglas D. Smith ,  David W. Knebelsberger ,  Myron Buer

    发明人： Mark Slamowitz ,  Douglas D. Smith ,  David W. Knebelsberger ,  Myron Buer

    IPC分类号： G11C7/06 ,  G11C8/16 ,  G11C7/00

    CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C7/067 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/063

    摘要： The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements and a differential sensing device or circuit. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and the sensing device. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects.

    摘要翻译： 本发明涉及一种多端口寄存器文件存储器或SRAM，它包括多个存储元件和其他同步或异步操作的电路。 存储元素以行和列排列并存储数据。 两个读端口对耦合到每个存储元件和差分感测装置或电路。 读取端口以隔离的方式耦合到存储元件，使得多个单元格能够以这样的行和列排列。 感测装置适于感测小的电压摆幅。 列复用电路耦合到每个列和感测装置。 随着电源电压由于总线掉落或电感效应而降低，性能不会异常降低。

    High voltage switch circuitry
    8.
    发明授权
    High voltage switch circuitry 有权
    高压开关电路

    公开(公告)号：US06901004B2

    公开(公告)日：2005-05-31

    申请号：US10856117

    申请日：2004-05-28

    申请人： Douglas D. Smith ,  Myron Buer ,  Bassem Radieddine

    发明人： Douglas D. Smith ,  Myron Buer ,  Bassem Radieddine

    IPC分类号： G11C17/16 ,  H01L23/525 ,  G11C11/00

    CPC分类号： H01L23/5256 ,  G11C17/16 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention relates to a high voltage switch used with a one-time programmable memory device and a method of setting a state of a one-time programmable memory device using such a high voltage switch. The memory device includes a plurality of one time programmable memory cells arranged in an array and adapted to be programmed using a high voltage, wherein each of the memory cells includes at least one storage element and two gated fuses connected to the storage element. A high voltage switch is connected to at least one of the memory cells and is adapted to switch in a high voltage.

    摘要翻译： 本发明涉及一次性可编程存储装置中使用的高电压开关和使用这种高电压开关来设定一次可编程存储装置的状态的方法。 存储器件包括以阵列布置并适于使用高电压编程的多个一次可编程存储器单元，其中每个存储器单元包括连接到存储元件的至少一个存储元件和两个门控保险丝。 高电压开关连接到至少一个存储单元并适于切换高电压。

    High voltage switch circuitry
    9.
    发明授权
    High voltage switch circuitry 有权
    高压开关电路

    公开(公告)号：US06693819B2

    公开(公告)日：2004-02-17

    申请号：US10041296

    申请日：2002-01-08

    申请人： Douglas D. Smith ,  Myron Buer ,  Bassem Radieddine

    发明人： Douglas D. Smith ,  Myron Buer ,  Bassem Radieddine

    IPC分类号： G11C1100

    CPC分类号： H01L23/5256 ,  G11C17/16 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention relates to a high voltage switch used with a one-time programmable memory device and a method of setting a state of a one-time programmable memory device using such a high voltage switch. The memory device includes a plurality of one time programmable memory cells arranged in an array and adapted to be programmed using a high voltage, wherein each of the memory cells includes at least one storage element and two gated fuses connected to the storage element. A high voltage switch is connected to at least one of the memory cells and is adapted to switch in a high voltage.

    摘要翻译： 本发明涉及一次性可编程存储装置中使用的高电压开关和使用这种高电压开关来设定一次可编程存储装置的状态的方法。 存储器件包括以阵列布置并适于使用高电压编程的多个一次可编程存储器单元，其中每个存储器单元包括连接到存储元件的至少一个存储元件和两个门控保险丝。 高电压开关连接到至少一个存储单元并适于切换高电压。