公开(公告)号：US20070025040A1

公开(公告)日：2007-02-01

申请号：US11332294

申请日：2006-01-17

申请人： Tong Tsai ,  Fu Chu ,  Shau Wang

发明人： Tong Tsai ,  Fu Chu ,  Shau Wang

IPC分类号： H02H3/20 ,  H05K3/20

CPC分类号： H01C7/027 ,  H01C17/0652 ,  H01C17/06586 ,  Y10T29/49126 ,  Y10T29/49128

摘要： The present invention is to provide a high voltage over-current protection device and a manufacturing method thereof, in which PTC polymers are cross-linked by chemical cross-linking. With the method of the present invention, the high voltage endurance of the PTC devices is enhanced. In addition, the internal stress and degradation of polymers caused by irradiation treatment are prevented.

摘要翻译： 本发明提供一种高电压过电流保护装置及其制造方法，其中PTC聚合物通过化学交联进行交联。 利用本发明的方法，提高了PTC器件的高耐压性。 此外，防止了由照射处理引起的聚合物的内应力和降解。

公开(公告)号：US20050130334A1

公开(公告)日：2005-06-16

申请号：US11046424

申请日：2005-01-27

申请人： Jun-Cheng Ko ,  Young-Tong Tsai

发明人： Jun-Cheng Ko ,  Young-Tong Tsai

IPC分类号： H01L21/00 ,  H01L21/60 ,  H01L21/768 ,  G01R31/26 ,  H01L21/4763 ,  H01L21/66

CPC分类号： H01L21/67253 ,  H01J37/32963 ,  H01L21/67069 ,  H01L21/76802 ,  H01L21/76897

摘要： A bias compensation self-aligned contact (SAC) etch endpoint detecting system is provided. The system includes an etch reactant chamber, an ESC power supply, and a signal processing computer. The etch reactant chamber includes an electrostatic chuck (ESC), a top electrode, and a bottom electrode. The ESC supports a substrate having an interlevel dielectric (ILD) layer to be etched. The ESC power supply is coupled to the ESC and is configured to function as a bias compensating power supply. The signal processing computer monitors a bias compensation signal generated by the ESC power supply. The etch process to be carried out in the etch reactant chamber is configured to be discontinued when the bias compensation signal is determined to have a previously ascertained characteristic evidencing an etch endpoint of the ILD layer.

摘要翻译： 提供偏置补偿自对准接触（SAC）蚀刻端点检测系统。 该系统包括蚀刻反应物室，ESC电源和信号处理计算机。 蚀刻反应物室包括静电卡盘（ESC），顶部电极和底部电极。 ESC支持具有待蚀刻的层间电介质（ILD）层的衬底。 ESC电源耦合到ESC，并配置为用作偏置补偿电源。 信号处理计算机监视由ESC电源产生的偏置补偿信号。 在蚀刻反应物室中进行的蚀刻工艺被配置为当偏置补偿信号被确定为具有证明ILD层的蚀刻端点的先前确定的特性时被停止。

公开(公告)号：US20060108566A1

公开(公告)日：2006-05-25

申请号：US11266217

申请日：2005-11-04

申请人： Yun Ma ,  Tong Tsai ,  Kuo Chen

发明人： Yun Ma ,  Tong Tsai ,  Kuo Chen

IPC分类号： H01B1/12

CPC分类号： H01B1/24 ,  H01C7/027

摘要： The present invention discloses a conductive composition comprising a plurality of polymers and at least one conductive filler. The polymers are compatible under a molecular size and the form of the conductive filler includes a flake. The conductive composition of the present invention owns better electrical characteristics than a conventional conductive composition that comprises a single polymer. The present invention further discloses an over-current protection device comprising two metal foils and a PTC (positive temperature coefficient; PTC) composition layer. The PTC composition layer contains the conductive composition.

摘要翻译： 本发明公开了一种包含多种聚合物和至少一种导电填料的导电组合物。 聚合物在分子尺寸下相容，并且导电填料的形式包括片状物。 本发明的导电组合物比包含单一聚合物的常规导电组合物具有更好的电特性。 本发明还公开了一种包括两个金属箔和PTC（正温度系数; PTC）组合物层的过电流保护装置。 PTC组合物层包含导电组合物。

公开(公告)号：US06188889B1

公开(公告)日：2001-02-13

申请号：US09153047

申请日：1998-09-15

申请人： Shyi-Tong Tsai

发明人： Shyi-Tong Tsai

IPC分类号： H04M300

CPC分类号： G08C17/02 ,  G08C19/28 ,  G08C2201/20

摘要： A radio transmitter includes a high frequency circuit for modulation and transmitting during a remote transmitting mode and for receiving and demodulation during a receiving learning mode, a LED indicator connected in series between the high frequency circuit and the power supply for transmitting indication and tuning indication, a single chip microcomputer for identification code checking and code encoding control, and a memory (EEPROM) for data storage.

摘要翻译： 无线电发射机包括用于在远程发射模式期间进行调制和发射的高频电路，以及用于在接收学习模式期间接收和解调的LED指示器，串联连接在高频电路和用于发送指示和调谐指示的电源之间的LED指示， 用于识别代码检查和代码编码控制的单片机，​​以及用于数据存储的存储器（EEPROM）。

公开(公告)号：US06057240A

公开(公告)日：2000-05-02

申请号：US55437

申请日：1998-04-06

申请人： Mei-Sheng Zhou ,  Jian-Hui Ye ,  Simon Chooi ,  Young-Tong Tsai

发明人： Mei-Sheng Zhou ,  Jian-Hui Ye ,  Simon Chooi ,  Young-Tong Tsai

IPC分类号： C11D1/04 ,  C11D1/68 ,  C11D1/70 ,  C11D3/30 ,  C11D11/00 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H05K3/06 ,  H01R13/502 ,  C11D9/00

CPC分类号： H01L21/02071 ,  B82Y10/00 ,  B82Y30/00 ,  C11D11/0047 ,  C11D3/30 ,  H01L21/31138 ,  H01L21/32136 ,  H05K3/064 ,  C11D1/04 ,  H05K2203/0793 ,  H05K2203/095

摘要： A method for forming a patterned metal layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a blanket metal layer. There is then formed over the blanket metal layer a patterned photoresist layer. There is then etched through use of a plasma etch method while employing the patterned photoresist layer as a photoresist etch mask layer the blanket metal layer to form a patterned metal layer. The patterned metal layer so formed has a metal impregnated carbonaceous polymer residue layer formed upon a sidewall of the patterned metal layer. There is then stripped from the patterned metal layer the patterned photoresist layer through use of an oxygen containing plasma while simultaneously oxidizing the metal impregnated carbonaceous polymer residue layer to form an oxidized metal impregnated polymer residue layer upon the sidewall of the patterned metal layer. There is then stripped from the sidewall of the patterned metal layer the oxidized metal impregnated polymer residue layer while employing an aqueous alkyl ammonium hydroxide based solution. The aqueous alkyl ammonium hydroxide based solution has incorporated therein a surfactant capable of forming a monolayer adsorbed upon the sidewall of the patterned metal layer.

摘要翻译： 一种用于在微电子制造中形成图案化金属层的方法。 首先提供了在微电子制造中使用的衬底。 然后在衬底上形成覆盖金属层。 然后在覆盖金属层上形成图案化的光致抗蚀剂层。 然后通过使用等离子体蚀刻方法蚀刻，同时使用图案化的光致抗蚀剂层作为光刻胶蚀刻掩模层，覆盖金属层以形成图案化的金属层。 如此形成的图案化金属层具有形成在图案化金属层的侧壁上的金属浸渍碳质聚合物残余层。 然后通过使用含氧等离子体从图案化的金属层剥离图案化的光刻胶层，同时对金属浸渍的碳质聚合物残余层进行氧化，以在图案化金属层的侧壁上形成氧化金属浸渍的聚合物残余物层。 然后从图案化金属层的侧壁剥离氧化金属浸渍的聚合物残余物层，同时使用基于烷基氢氧化铵的水溶液。 基于烷基氢氧化铵的水溶液溶液中加入了能够形成单层吸附在图案化金属层的侧壁上的表面活性剂。

公开(公告)号：US5792708A

公开(公告)日：1998-08-11

申请号：US611585

申请日：1996-03-06

申请人： Mei Sheng Zhou ,  Lap Chan ,  Young-Tong Tsai

发明人： Mei Sheng Zhou ,  Lap Chan ,  Young-Tong Tsai

IPC分类号： H01L21/3213 ,  H01L21/08

CPC分类号： H01L21/32137

摘要： A method for forming a residue free patterned polysilicon layer upon a high step height patterned substrate layer. First, there is provided a semiconductor substrate having formed thereon a high step height patterned substrate layer. Formed upon the high step height patterned substrate layer is a polysilicon layer, and formed upon the polysilicon layer is a patterned photoresist layer. The patterned photoresist layer exposes portions of the polysilicon layer at a lower step level of the high step height patterned substrate layer. The polysilicon layer is then patterned through the patterned photoresist layer as an etch mask employing an anisotropic first etch process to yield a patterned polysilicon layer upon the surface of the high step height patterned substrate layer and polysilicon residues at the lower step level of the high step height patterned substrate layer. The anisotropic first etch process is a Reactive Ion Etch (RIE) anisotropic first etch process which simultaneously passivates the exposed sidewall edges of the patterned polysilicon layer. Finally, the polysilicon residues formed at the lower step level of the high step height patterned substrate layer are removed through an isotropic second etch process. The isotropic second etch process is a Reactive Ion Etch (RIE) isotropic second etch process which employs hydrogen bromide (HBr) and sulfur hexafluoride (SF6) as the reactant gases.

摘要翻译： 一种用于在高台阶高度图案化衬底层上形成无残留图案化多晶硅层的方法。 首先，提供在其上形成有高台阶高度图案化基板层的半导体基板。 形成在高台阶高度图案化衬底层上的是多晶硅层，并且在多晶硅层上形成图案化的光致抗蚀剂层。 图案化的光致抗蚀剂层在高阶高度图案化衬底层的较低台阶处暴露多晶硅层的部分。 然后通过图案化的光致抗蚀剂层将多晶硅层图案化为使用各向异性第一蚀刻工艺的蚀刻掩模，以在高阶高度图案化衬底层的表面上产生图案化多晶硅层，并在高级步骤的较低级别处产生多晶硅残余物 高度图案化衬底层。 各向异性第一蚀刻工艺是反应离子蚀刻（RIE）各向异性第一蚀刻工艺，其同时钝化图案化多晶硅层的暴露的侧壁边缘。 最后，通过各向同性的第二蚀刻工艺去除在高阶高度图案化衬底层的较低台阶处形成的多晶硅残余物。 各向同性第二蚀刻工艺是使用溴化氢（HBr）和六氟化硫（SF6）作为反应气体的反应离子蚀刻（RIE）各向同性第二蚀刻工艺。

公开(公告)号：US06861362B2

公开(公告)日：2005-03-01

申请号：US09895566

申请日：2001-06-29

申请人： Jun-Cheng Ko ,  Young-Tong Tsai

发明人： Jun-Cheng Ko ,  Young-Tong Tsai

IPC分类号： H01L21/00 ,  H01L21/60 ,  H01L21/768 ,  H01L21/302

CPC分类号： H01L21/67253 ,  H01J37/32963 ,  H01L21/67069 ,  H01L21/76802 ,  H01L21/76897

摘要： A method for enhancing the fabrication process of a self-aligned contact (SAC) structure is provided. The method includes forming a transistor structure on a surface of a substrate. The method also includes forming a dielectric layer directly over the surface of the substrate without forming an etch stop layer on the surface of the substrate. Also included in the method is plasma etching a contact hole through the dielectric layer in a plasma processing chamber. The method also includes monitoring a bias compensation voltage of the plasma processing chamber during the plasma etching process and discontinuing the plasma etching process upon detecting an endpoint signaling change in the bias compensation voltage.

摘要翻译： 提供了一种用于增强自对准接触（SAC）结构的制造工艺的方法。 该方法包括在衬底的表面上形成晶体管结构。 该方法还包括在衬底的表面上直接形成电介质层，而不在衬底的表面上形成蚀刻停止层。 还包括在等离子体处理室中的等离子体蚀刻穿过介电层的接触孔。 该方法还包括在等离子体蚀刻过程期间监测等离子体处理室的偏置补偿电压，并且在检测到偏置补偿电压中的端点信号变化时停止等离子体蚀刻工艺。

公开(公告)号：US06559049B2

公开(公告)日：2003-05-06

申请号：US10210612

申请日：2002-07-31

申请人： Lawrence Chen ,  Chang-Tai Chiao ,  Young Tong Tsai ,  Francis Ko ,  Chuan-Kai Lo

发明人： Lawrence Chen ,  Chang-Tai Chiao ,  Young Tong Tsai ,  Francis Ko ,  Chuan-Kai Lo

IPC分类号： H01L214763

CPC分类号： H01L21/31116 ,  H01L21/31138 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813

摘要： The present invention reveals a semiconductor dual damascene etching process, which uses a confined plasma etching chamber to integrate all dual damascene steps such as via hole etching, photoresist stripping and barrier layer removal which originally performed in various reactors as a continuous procedure in the confined plasma chamber. The confined plasma chamber including a confinement ring surrounding a wafer and an anti-etching upper electrode plate performs the steps mentioned above under clean mode. The present invention can not only reduce the time period required by the semiconductor dual damascene process but also greatly reduce the manufacturing cost.

摘要翻译： 本发明揭示了半导体双镶嵌蚀刻工艺，其使用限定等离子体蚀刻室来整合所有双镶嵌步骤，例如通孔蚀刻，光致抗蚀剂剥离和阻挡层去除，其最初在各种反应器中作为连续过程在约束等离子体 房间。 包含晶圆周围的限制环和防蚀刻上电极板的受限等离子体室在清洁模式下进行上述步骤。 本发明不仅可以减少半导体双镶嵌工艺所需的时间，而且可以大大降低制造成本。