公开(公告)号：US5699005A

公开(公告)日：1997-12-16

申请号：US563173

申请日：1995-11-27

申请人： Andreas Menkhoff ,  Ulrich Theus

发明人： Andreas Menkhoff ,  Ulrich Theus

IPC分类号： G06F1/025 ,  G06F1/04 ,  H03C3/00 ,  H03K3/84 ,  H03K5/13 ,  H03K5/133 ,  H03K7/06 ,  H03K1/04

CPC分类号： H03K7/06 ,  G06F1/025 ,  G06F1/04 ,  H03K5/133 ,  H04B2215/064 ,  H04B2215/067

摘要： A clock generator circuit for clock controlled electronic devices, which causes minimal electromagnetic interference in adjacent electronic equipment. The clock generator circuit includes a clock source for generating a basic clock signal having a predetermined frequency. The basic clock signal defines a reference clock signal having a period T. A phase modulator coupled to the clock source for producing a system clock signal by delaying the basic clock signal. A signal source coupled to the phase modulator, which controls the phase modulator so that the system clock signal is delayed with respect to the reference clock signal by a time period less than half of the period T of the reference clock signal.

摘要翻译： 用于时钟控制电子设备的时钟发生器电路，其在相邻电子设备中引起最小的电磁干扰。 时钟发生器电路包括用于产生具有预定频率的基本时钟信号的时钟源。 基本时钟信号定义具有周期T的参考时钟信号。相位调制器，耦合到时钟源，用于通过延迟基本时钟信号产生系统时钟信号。 耦合到相位调制器的信号源，其控制相位调制器，使得系统时钟信号相对于参考时钟信号延迟小于参考时钟信号的周期T的一半的时间周期。

公开(公告)号：US20100109744A1

公开(公告)日：2010-05-06

申请号：US12613959

申请日：2009-11-06

申请人： Martin Czech ,  Juergen Giehl ,  Ulrich Theus

发明人： Martin Czech ,  Juergen Giehl ,  Ulrich Theus

IPC分类号： H03L5/00

CPC分类号： H03K3/356113 ,  H03K19/018521

摘要： A level shifter for converting an input signal (in) from a first operating voltage range (I) having a first ground potential (VSS1) and a first operating potential (VDD1) into an output signal (out) in a second operating voltage range (II) having a second ground potential (VSS2) and a second operating potential (VDD2). An input circuit (1) receives the input signal and an output circuit (2) provides the output signal (out), where the input circuit includes a parallel circuit made up by a first cascode circuit and a second cascode circuit, and the first and second cascode circuits each being formed by a first transistor in the source circuit and a second transistor in the gate circuit, a dynamic control being provided for the second transistors.

摘要翻译： 一种电平移位器，用于将具有第一接地电位（VSS1）和第一操作电位（VDD1）的第一工作电压范围（I）的输入信号（in）转换成第二工作电压范围内的输出信号（out） II）具有第二接地电位（VSS2）和第二工作电位（VDD2）。 输入电路（1）接收输入信号，并且输出电路（2）提供输出信号（out），其中输入电路包括由第一共源共栅电路和第二共源共栅电路组成的并联电路，第一和 每个由源极电路中的第一晶体管和栅极电路中的第二晶体管形成的第二共源共栅电路，为第二晶体管提供动态控制。

公开(公告)号：US20100109743A1

公开(公告)日：2010-05-06

申请号：US12613901

申请日：2009-11-06

申请人： Martin Czech ,  Juergen Giehl ,  Ulrich Theus

发明人： Martin Czech ,  Juergen Giehl ,  Ulrich Theus

IPC分类号： H03L5/00

CPC分类号： H03K3/356113 ,  H03K17/102

摘要： A level shifter for converting an input signal (in) from a first operating voltage range (I) having a first ground potential (VSS1) and a first operating potential (VDD1) in a second operating voltage range (II) having a second ground potential (VSS2) and a second operating potential (VDD2), having an input circuit to which the input signal (in) may be applied and an output circuit at which the output signal (out) may be picked off, the input circuit having at least one native transistor.

摘要翻译： 一种电平移位器，用于在具有第二接地电位的第二工作电压范围（II）中将具有第一接地电位（VSS1）和第一操作电位（VDD1）的第一工作电压范围（I）的输入信号（in） （VSS2）和第二工作电位（VDD2），其具有可以被施加输入信号（in）的输入电路和输出电路，输出信号（out）可以在该输出电路被拾取，输入电路至少具有 一个原生晶体管。

公开(公告)号：US5912581A

公开(公告)日：1999-06-15

申请号：US919455

申请日：1997-08-28

申请人： Burkhard Giebel ,  Ulrich Theus

发明人： Burkhard Giebel ,  Ulrich Theus

IPC分类号： H05K9/00 ,  H01L21/822 ,  H01L27/04 ,  H03K19/003 ,  H01L21/82

CPC分类号： H03K19/00346

摘要： Spurious-emission-reducing terminal configuration for an integrated circuit, particularly a monolithic integrated circuit, operable within an unshielded board network, the integrated circuit being divided into a first subcircuit, which has essentially radio-frequency current components, and a second subcircuit, which has essentially low-frequency current components, the separation also extending to the internal supply lines and supply contact pads. The second subcircuit includes driver circuits which are connected to I/O lines on the board network. On the grounded side, the first and second supply current paths are interconnected within the integrated circuit by a low-resistance and low-inductance connection to establish a ground point.

摘要翻译： 用于在非屏蔽板网络内可操作的集成电路，特别是单片集成电路的杂散发射减少端子配置，该集成电路被分成具有实质上是射频电流分量的第一子电路和第二子电路，其中 具有基本的低频电流分量，分离也延伸到内部电源线并提供接触焊盘。 第二支路包括连接到电路板网络上的I / O线路的驱动电路。 在接地侧，第一和第二电源电流路径通过低电阻和低电感连接在集成电路内互连以建立接地点。

公开(公告)号：US5047727A

公开(公告)日：1991-09-10

申请号：US583267

申请日：1990-09-14

申请人： Ulrich Theus

发明人： Ulrich Theus

IPC分类号： H03F3/34 ,  H03F1/30 ,  H03F3/347 ,  H03F3/45

CPC分类号： H03F1/303

摘要： An offset-voltage-balancing operation amplifier for difference signals includes an auxiliary and a main amplifier, each having a difference input and an auto-zero input. To provide offset balancing, the auto-zero inputs are connected to the potentials of two integrated storage capacitors. The difference input of the auxiliary amplifier can be short-circuited via first and second switching means, and the two storage capacitors are connected to the output of the auxiliary amplifier via third and fourth switching means. The sensitivity of the auto-zero inputs is less than the sensitivity of the difference inputs.

摘要翻译： 用于差分信号的偏移电压平衡运算放大器包括辅助和主放大器，每个具有差分输入和自动归零输入。 为了提供偏移平衡，自动归零输入连接到两个集成存储电容器的电位。 辅助放大器的差分输入可以通过第一和第二开关装置短路，并且两个存储电容器经由第三和第四开关装置连接到辅助放大器的输出端。 自动归零输入的灵敏度小于差分输入的灵敏度。

公开(公告)号：US4947171A

公开(公告)日：1990-08-07

申请号：US321593

申请日：1989-03-10

申请人： Heinrich Pfeifer ,  Werner Reich ,  Ulrich Theus

发明人： Heinrich Pfeifer ,  Werner Reich ,  Ulrich Theus

IPC分类号： H03M1/60 ,  H03M3/04

CPC分类号： H03M3/372 ,  H03M3/458

摘要： In a pulse-density D/A or A/D converter, improved averaging of a pulse-density-modulated (PDM) signal in the presence of a jittering clock signal is achieved by applying the PDM signal to the serial input of an n-stage shift register whose parallel output serves to control n state signals. The shift register is driven by the clock signal. The n state signals are combined into a sum signal which feeds a low-pass filter. In preferred embodiments, the n state signals are weighted and/or isolated from the respective previous state and the following state by means of gate circuits.

摘要翻译： 在脉冲密度D / A或A / D转换器中，在存在抖动时钟信号的情况下，脉冲密度调制（PDM）信号的改进的平均通过将PDM信号施加到n- 其并行输出用于控制n个状态信号。 移位寄存器由时钟信号驱动。 n状态信号被组合成馈送低通滤波器的和信号。 在优选实施例中，n状态信号通过门电路从相应的先前状态和随后的状态被加权和/或隔离。

公开(公告)号：US4817030A

公开(公告)日：1989-03-28

申请号：US28251

申请日：1987-03-20

申请人： Peter Lee ,  Ulrich Theus

发明人： Peter Lee ,  Ulrich Theus

IPC分类号： G06F7/501 ,  G06F7/50 ,  G06F7/503 ,  G06F7/508

CPC分类号： G06F7/501 ,  G06F2207/3876

摘要： To a prior art CMOS full-adder stage having sixteen transistors, a static inverter is added which consists of a P-type transistor and an N-type transistor, and the series combination (sc) of P- and N-type transistors is wired symmetrically. This increases the processing frequency, because the carry-signal path is no longer loaded by the four transistors contributing to the summation.

摘要翻译： 对于具有十六个晶体管的现有技术的CMOS全加器级，添加由P型晶体管和N型晶体管组成的静态逆变器，并且P型和N型晶体管的串联组合（sc）被布线 对称地。 这增加了处理频率，因为进位信号路径不再由有助于求和的四个晶体管加载。

公开(公告)号：US4803657A

公开(公告)日：1989-02-07

申请号：US43384

申请日：1987-04-28

申请人： Burkhard Giebel ,  Ulrich Theus

发明人： Burkhard Giebel ,  Ulrich Theus

IPC分类号： G11C7/00 ,  G06F5/08 ,  G11C19/00 ,  G11C19/18 ,  G11C19/28

CPC分类号： G06F5/08 ,  G11C19/188

摘要： A delay line digital memory is organized into n signal branches (z.sub.1 . . . z.sub.n), each with m cells which form a serial data or signal flow path. Each cell is comprised of a transfer transistor t with a subsequently following level restorer, regenerator, or buffer circuit p which, however, is omitted in the last cell. Furthermore, n clock signals (s.sub.l . . . s.sub.n) are provided whose frequency (or repetition rate) equals one n-th of the data rate of the digital input signals, and whose effective pulses follow each other in temporal serial succession within one period of the data rate. Clocking (or activation) by clock signals (s.sub.1 . . . s.sub.n) is chosen so that in the first signal branch (z.sub.1) the first transistor is fed with the last clock signal (s.sub.n); in the second signal branch, the first transistor is fed with the next to last clock signal (s.sub.n-1); in the next to last signal branch (z.sub.n-1), the first transistor is fed with the second clock signal (s.sub.2); and in the 1st signal branch (z.sub.n) the first transistor is fed with the first clock signal (s.sub.1) at its gate. The remaining transistors of each signal branch are then fed in the sense of a descending clock-signal numbering order. Both the inputs and outputs of the signal branches are assembled or led together to either the signal input (s.sub.e) or the signal output (s.sub.a). This arrangement results in a considerable saving of space in the case of a monolithic integration compared to the cases in which shift registers or dynamic random access memories (DRAMs) are employed. The effective length of the storage time can be reduced in increments corresponding to the magnitude of the period of the data rate of the input signal.

摘要翻译： 延迟线数字存储器被组织成n个信号分支（z1 ... zn），每个信号分支具有形成串行数据或信号流路径的m个单元。 每个单元由具有随后的下一级恢复器，再生器或缓冲电路p的传输晶体管t组成，然而在最后一个单元中省略。 此外，提供了n个时钟信号（s1·sn），其频率（或重复频率）等于数字输入信号的数据速率的十分之一，并且其有效脉冲在一个周期内以时间序列连续相互追随 的数据速率。 选择由时钟信号（s1，...）进行的时钟（或激活），使得在第一信号分支（z1）中，第一晶体管馈送最后的时钟信号（sn）; 在第二信号分支中，第一晶体管馈送有下一个最后的时钟信号（sn-1）; 在下一个信号分支（zn-1）中，第一晶体管馈送第二时钟信号（s2）; 并且在第一信号分支（zn）中，第一晶体管在其门处馈送有第一时钟信号（s1）。 然后每个信号分支的剩余晶体管以降序的时钟信号编号顺序被馈送。 信号分支的输入和输出都被组合或者被引导到信号输入（se）或信号输出（sa）。 与使用移位寄存器或动态随机存取存储器（DRAM）的情况相比，这种布置导致在单片集成的情况下相当大的节省空间。 存储时间的有效长度可以以与输入信号的数据速率的周期的大小对应的增量减小。

公开(公告)号：US08344784B2

公开(公告)日：2013-01-01

申请号：US12960806

申请日：2010-12-06

申请人： Martin Czech ,  Ulrich Theus

发明人： Martin Czech ,  Ulrich Theus

IPC分类号： H03L5/00

CPC分类号： H03K19/018585

摘要： A method and circuit arrangement is provided for controlling switching transistors of an integrated circuit, with a bridge circuit and with a control unit, which is designed and/or has a program so that the control unit is designed as a measuring device and measures a bridge voltage of the bridge circuit, outputs an adjusting signal for adjusting a component of a bridge circuit, and outputs a control signal for activating the switching transistors. When the bridge circuit) has a branch with a resistor network and a transistor connected in series, and the control unit is designed and/or has a program so that the adjusting signal for adjusting a resistance value of the resistor network is switchable as the component dependent on the bridge voltage.

摘要翻译： 提供一种用于控制集成电路的开关晶体管的方法和电路装置，具有桥接电路和控制单元，其被设计和/或具有程序，使得控制单元被设计为测量装置并测量桥 输出用于调整桥接电路的分量的调整信号，并输出用于激活开关晶体管的控制信号。 当桥式电路）具有串联连接的电阻网络和晶体管的分支，并且控制单元被设计和/或具有程序，使得用于调整电阻网络的电阻值的调整信号可以作为组件 取决于桥电压。

公开(公告)号：US20110133782A1

公开(公告)日：2011-06-09

申请号：US12960806

申请日：2010-12-06

申请人： Martin Czech ,  Ulrich Theus

发明人： Martin Czech ,  Ulrich Theus

IPC分类号： G01R19/165 ,  H03K17/687

CPC分类号： H03K19/018585

摘要： A method and circuit arrangement is provided for controlling switching transistors of an integrated circuit, with a bridge circuit and with a control unit, which is designed and/or has a program so that the control unit is designed as a measuring device and measures a bridge voltage of the bridge circuit, outputs an adjusting signal for adjusting a component of a bridge circuit, and outputs a control signal for activating the switching transistors. When the bridge circuit) has a branch with a resistor network and a transistor connected in series, and the control unit is designed and/or has a program so that the adjusting signal for adjusting a resistance value of the resistor network is switchable as the component dependent on the bridge voltage.

摘要翻译： 提供一种用于控制集成电路的开关晶体管的方法和电路装置，具有桥接电路和控制单元，其被设计和/或具有程序，使得控制单元被设计为测量装置并测量桥 输出用于调整桥接电路的分量的调整信号，并输出用于激活开关晶体管的控制信号。 当桥式电路）具有串联连接的电阻网络和晶体管的分支，并且控制单元被设计和/或具有程序，使得用于调整电阻网络的电阻值的调整信号可以作为组件 取决于桥电压。