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    Clock generating circuit capable of generating internal clock accurately synchronized with external clock
    2.
    发明授权
    Clock generating circuit capable of generating internal clock accurately synchronized with external clock 失效
    时钟发生电路能够产生与外部时钟精确同步的内部时钟

    公开(公告)号：US06724228B2

    公开(公告)日：2004-04-20

    申请号：US10359679

    申请日：2003-02-07

    申请人： Yasuhiro Kashiwazaki

    发明人： Yasuhiro Kashiwazaki

    IPC分类号： H03K513

    CPC分类号： H03L7/0805 ,  G06F1/12 ,  H03K5/131 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/0814 ,  H03L7/089

    摘要： A phase difference between a feedback clock signal corresponding to an internal clock signal generated via a variable delay line and a buffered clock signal corresponding to an external clock signal is detected by a phase detector, and a result of detection is transferred via a shifting circuit. When a down signal from the shifting circuit is activated by a delay control circuit, the down instruction signal is forcibly maintained to be active for a predetermined clock cycle period. When the down instruction signal becomes inactive from the active state, a count control circuit sets a count unit of the counting circuit to the minimum value. The delay amount of the variable delay line is set according to an output count bit of the counting circuit. Therefore, it is possible to reduce the number of clock cycles required until an internal clock signal is synchronized in phase with the external clock signal.

    摘要翻译： 通过相位检测器检测与经由可变延迟线产生的内部时钟信号相对应的反馈时钟信号与对应于外部时钟信号的缓冲时钟信号之间的相位差，经由移位电路传送检测结果。 当来自移位电路的下降信号被延迟控制电路激活时，下降指令信号被强制地保持在预定的时钟周期周期中是有效的。 当下降指令信号从激活状态变为无效时，计数控制电路将计数电路的计数单元设置为最小值。 根据计数电路的输出计数位设定可变延迟线的延迟量。 因此，可以减少所需的时钟周期数，直到内部时钟信号与外部时钟信号同步。

    Semiconductor memory device permitting control of internal power supply voltage in packaged state
    3.
    发明授权
    Semiconductor memory device permitting control of internal power supply voltage in packaged state 失效
    半导体存储器件允许在封装状态下控制内部电源电压

    公开(公告)号：US06853592B2

    公开(公告)日：2005-02-08

    申请号：US10642213

    申请日：2003-08-18

    申请人： Yasuhiro Kashiwazaki

    发明人： Yasuhiro Kashiwazaki

    IPC分类号： G01R31/28 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  G11C29/50 ,  G11C7/00

    CPC分类号： G11C5/14

    摘要： A selector selects one standard voltage from among divided voltages from a voltage dividing circuit and a reference voltage from a reference voltage generating circuit, in accordance with a test mode enable signal and a reference voltage select signal. An internal voltage generating circuit receives the standard voltage from the selector and generates an internal power supply voltage.

    摘要翻译： 选择器根据测试模式使能信号和参考电压选择信号从分压电路和参考电压产生电路的参考电压中选择一个标准电压。 内部电压产生电路从选择器接收标准电压并产生内部电源电压。

    Semiconductor memory device capable of executing refresh operation according to refresh space
    4.
    发明授权
    Semiconductor memory device capable of executing refresh operation according to refresh space 失效

    公开(公告)号：US06819618B2

    公开(公告)日：2004-11-16

    申请号：US10697097

    申请日：2003-10-31

    申请人： Yasuhiro Kashiwazaki

    发明人： Yasuhiro Kashiwazaki

    IPC分类号： G11C720

    CPC分类号： G11C11/40622 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4067

    摘要： A semiconductor memory device includes a memory having a predetermined number of divided memory spaces, a register that stores data indicating whether a refresh operation is required or not with respect to each memory space, a row address counter that, with reference to the register, counts up an address while skipping an address requiring no refresh operation, to thereby generate an address of the memory space to be refreshed, and a refresh cycle generating circuit that with reference to the register 15, generates a refresh cycle with a cycle which varies according to the number of the memory space requiring the refresh operation.

    Semiconductor device having phase error improved DLL circuit mounted thereon
    8.
    发明授权
    Semiconductor device having phase error improved DLL circuit mounted thereon 失效
    具有安装在其上的相位误差改善的DLL电路的半导体器件

    公开(公告)号：US06721232B2

    公开(公告)日：2004-04-13

    申请号：US10172908

    申请日：2002-06-18

    申请人： Yasuhiro Kashiwazaki

    发明人： Yasuhiro Kashiwazaki

    IPC分类号： G11C800

    CPC分类号： G11C8/18

    摘要： Two delay lines included in a DLL circuit receive clock signals complementary to each other to output complementary clock signals CLKP and CLKN for data output. A power supply generation circuit applying a power supply to the two delay lines is arranged at an equivalent position from the two delay line. An equal potential is supplied to the two delay lines by, for example, setting lengths of two power supply lines from a branch point equal to each other. By doing so, delay time of one delay line can be set equal to delay time of the other delay line and a phase error between clock signals CLKP and CLKN can be reduced. Therefore, a semiconductor device on which the DLL circuit having the improved phase error is mounted can be provided.

    摘要翻译： 包括在DLL电路中的两个延迟线接收彼此互补的时钟信号，以输出用于数据输出的互补时钟信号CLKP和CLKN。 将电源施加到两个延迟线的电源产生电路被布置在距离两个延迟线的等效位置。 通过例如从相互相等的分支点设定两条电源线的长度，向两条延迟线提供相等的电位。 通过这样做，可以将一个延迟线的延迟时间设置为等于另一个延迟线的延迟时间，并且可以减小时钟信号CLKP和CLKN之间的相位误差。 因此，可以提供其上安装有改进的相位误差的DLL电路的半导体器件。

    Semiconductor memory device capable of adjusting phase of output data and memory system using the same
    9.
    发明授权
    Semiconductor memory device capable of adjusting phase of output data and memory system using the same 失效

    公开(公告)号：US06570815B2

    公开(公告)日：2003-05-27

    申请号：US09973886

    申请日：2001-10-11

    申请人： Yasuhiro Kashiwazaki

    发明人： Yasuhiro Kashiwazaki

    IPC分类号： G11C800

    CPC分类号： G11C7/1066 ,  G11C7/1045 ,  G11C7/1051

    摘要： In a DLL circuit of a DDR SDRAM, in addition to a replica buffer for compensating delay in an output buffer, a replica buffer for compensating flight time is provided. The phase of a clock signal CLKP outputted to the outside so as to be locked with a clock signal BUFFCLK can be adjusted in accordance with a control signal b[1:0]. For a controller receiving data in a lump from a plurality of semiconductor memory devices, the arriving timings of data from the semiconductor memory devices can be aligned. Therefore, it is unnecessary to capture data in response to a data strobe signal DQS, so that burden on the controller is lessened.