公开(公告)号：US07932183B2

公开(公告)日：2011-04-26

申请号：US11934301

申请日：2007-11-02

申请人： Yasuyoshi Itoh ,  Masami Hayashi

发明人： Yasuyoshi Itoh ,  Masami Hayashi

IPC分类号： H01L21/302

CPC分类号： H01L27/1288 ,  G03F7/40 ,  H01L21/0273 ,  H01L27/1214

摘要： A method of manufacturing a multilayer thin film pattern includes forming a metal film over a substrate, forming a second thin film over the metal film, forming a resist pattern over the second thin film, etching the second thin film using the resist pattern as a mask, transforming the resist pattern using an organic solvent or a RELACS agent to cover an edge face of the etched second thin film and etching the metal film while the edge face of the second thin film is covered with the resist pattern.

摘要翻译： 一种制造多层薄膜图案的方法包括在基板上形成金属膜，在金属膜上形成第二薄膜，在第二薄膜上形成抗蚀剂图案，使用抗蚀剂图案作为掩模蚀刻第二薄膜 使用有机溶剂或RELACS剂转印抗蚀剂图案以覆盖被蚀刻的第二薄膜的边缘面，并且在第二薄膜的边缘面被抗蚀剂图案覆盖的同时蚀刻金属膜。

公开(公告)号：US07709841B2

公开(公告)日：2010-05-04

申请号：US11420956

申请日：2006-05-30

申请人： Yasuyoshi Itoh ,  Toru Takeguchi

发明人： Yasuyoshi Itoh ,  Toru Takeguchi

IPC分类号： H01L29/04

CPC分类号： H01L29/78675 ,  H01L27/1296 ,  H01L29/78666

摘要： An island-like semiconductor layer is formed on a main surface of an insulating substrate. A side wall of the island-like semiconductor layer is made substantially perpendicular to the insulating substrate. An insulating film is formed along the side wall of the semiconductor layer. The insulating film is formed to include a slanted face and have a sectional shape in which a width measured from the side wall of the semiconductor layer decreases as a distance to a bottom increases. A gate insulating film can be formed on the semiconductor layer with good step coverage because of inclusion of the insulating film, to preclude a possibility of causing disconnection of a gate electrode. Also, a thickness of a portion of the semiconductor layer in which a channel region is formed is uniform, to obtain stable transistor characteristics.

摘要翻译： 在绝缘基板的主表面上形成岛状半导体层。 岛状半导体层的侧壁基本上垂直于绝缘基板。 沿半导体层的侧壁形成绝缘膜。 绝缘膜形成为包括倾斜面，并且具有从半导体层的侧壁测量的宽度随着与底部距离的增加而减小的截面形状。 由于包含绝缘膜，可以在半导体层上形成具有良好阶梯覆盖的栅极绝缘膜，以防止导致栅电极断开的可能性。 此外，其中形成沟道区的半导体层的一部分的厚度是均匀的，以获得稳定的晶体管特性。

公开(公告)号：US20090121227A1

公开(公告)日：2009-05-14

申请号：US12266064

申请日：2008-11-06

申请人： Yasuyoshi ITOH ,  Toshio Araki

发明人： Yasuyoshi ITOH ,  Toshio Araki

IPC分类号： H01L29/04 ,  H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： A method of manufacturing a thin film transistor array substrate according to the present invention includes: forming a pattern made of a first conductive film; stacking a gate insulating film, a semiconductor layer, and a resist in the stated order; forming a resist pattern having a step structure in a thickness direction; forming an exposed area of the first conductive film and a pattern of the semiconductor layer by using the resist pattern; forming a pattern made of a second conductive film in contact with the first conductive film in the exposed area of the first conductive film; and forming a pattern made of a third conductive film. The first conductive film forms a gate electrode, and the second conductive film forms each of a source electrode and a drain electrode. The third conductive film forms a pixel electrode, and the second conductive film is coated with an upper-layer film.

摘要翻译： 根据本发明的制造薄膜晶体管阵列基板的方法包括：形成由第一导电膜制成的图案; 以所述顺序层叠栅极绝缘膜，半导体层和抗蚀剂; 在厚度方向上形成具有台阶结构的抗蚀剂图案; 通过使用抗蚀剂图案形成第一导电膜的暴露区域和半导体层的图案; 在所述第一导电膜的暴露区域中形成与所述第一导电膜接触的第二导电膜形成的图案; 以及形成由第三导电膜制成的图案。 第一导电膜形成栅电极，第二导电膜形成源电极和漏电极。 第三导电膜形成像素电极，第二导电膜涂覆有上层膜。

公开(公告)号：US20080017865A1

公开(公告)日：2008-01-24

申请号：US11765103

申请日：2007-06-19

申请人： Yasuyoshi Itoh ,  Atsunori Nishiura

发明人： Yasuyoshi Itoh ,  Atsunori Nishiura

IPC分类号： H01L29/04 ,  H01L21/8238

CPC分类号： H01L27/12 ,  H01L29/42384 ,  H01L29/78612 ,  H01L29/78696

摘要： A thin film transistor substrate includes a thin film transistor of a first conductivity type, a semiconductor layer having a channel region of the first conductivity type placed between the source/drain regions, a gate electrode formed to an opposite face to the semiconductor layer with an gate insulating film interposed therebetween, an opening in the gate electrode corresponding to both edges in a channel width direction of the channel region. In the channel region corresponding to the opening, a highly concentrated impurity region having a higher impurity concentration of the first conductivity type than the channel corresponding to the gate electrode is formed.

摘要翻译： 薄膜晶体管衬底包括第一导电类型的薄膜晶体管，具有位于源极/漏极区之间的具有第一导电类型的沟道区的半导体层，形成在与半导体层相反的面上的栅电极， 栅极绝缘膜之间，栅极电极中的开口对应于沟道区域的沟道宽度方向上的两个边缘。 在与开口对应的沟道区域中，形成了比与栅电极对应的沟道的第一导电类型的杂质浓度高的高浓度杂质区。

公开(公告)号：US20070190724A1

公开(公告)日：2007-08-16

申请号：US11690704

申请日：2007-03-23

申请人： Yasuyoshi Itoh ,  Shuuichi Ueno ,  Haruo Furuta ,  Natsuo Ajika

发明人： Yasuyoshi Itoh ,  Shuuichi Ueno ,  Haruo Furuta ,  Natsuo Ajika

IPC分类号： H01L21/336

CPC分类号： H01L29/66833 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/42352 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7833 ,  H01L29/7923

摘要： It is an object to provide a semiconductor device capable of holding multibit information in one memory cell also when scaling for a nonvolatile memory progresses, and a method of manufacturing the semiconductor device. A trench (TRI) is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film (122) of a gate insulating film (120) which interpose the trench (TR1) are caused to function as first and second electric charge holding portions capable of holding electric charges (CH1) and (CH2). In the case in which the electric charges (CH1) are trapped and the electric charges (CH2) are then trapped, thus, a portion (130a) of a gate electrode (130) in the trench (TR1) functions as a shield. If a fixed potential is given to the gate electrode (130), the second electric charge holding portion is not influenced by an electric field (EF1) induced by the electric charges (CH1) so that the trapping of the electric charges (CH2) is not inhibited.

摘要翻译： 本发明的目的是提供一种能够在非易失性存储器的缩放进行时能够在一个存储单元中保持多位信息的半导体器件，以及半导体器件的制造方法。 在MONOS晶体管的沟道部分中形成沟槽（TRI）。 然后，使位于沟槽（TR1）的栅极绝缘膜（120）的氮化硅膜（122）中的源极侧部分和漏极侧部分作为能够保持的第一和第二电荷保持部 电荷（CH 1）和（CH 2）。 在电荷（CH 1）被捕获并且电荷（CH 2）然后被捕获的情况下，因此，沟槽（TR 1）中的栅电极（130）的部分（130a）用作 一个盾牌 如果向栅电极（130）施加固定电位，则第二电荷保持部不受电荷（CH 1）引起的电场（EF 1）的影响，使得电荷（CH 2）不被抑制。

公开(公告)号：US06383884B1

公开(公告)日：2002-05-07

申请号：US09496057

申请日：2000-02-02

申请人： Katsuomi Shiozawa ,  Takashi Kuroi ,  Yasuyoshi Itoh ,  Katsuyuki Horita

发明人： Katsuomi Shiozawa ,  Takashi Kuroi ,  Yasuyoshi Itoh ,  Katsuyuki Horita

IPC分类号： H01L21336

CPC分类号： H01L29/66545 ,  H01L21/28247 ,  H01L29/66537

摘要： A semiconductor device includes a silicon substrate (1), a pair of isolating insulation films (9), a channel region (2), a pair of source/drain regions (3), a pair of silicon oxide films (4) formed on an upper surface of the silicon substrate (1) so as to overlie the source/drain regions (3), and a gate structure (8) formed in a first recess defined by the upper surface of the silicon substrate (1) over the channel region (2) and side surfaces of the pair of silicon oxide films (4). The gate structure (8) includes a gate oxide film (5) formed on the upper surface of the silicon substrate (1), a pair of silicon oxide films (6) formed on lower part of the side surfaces of the pair of silicon oxide films (4), and a metal film (7) filling a second recess surrounded by upper part of the side surfaces of the silicon oxide films (4), the silicon oxide films (6) and the gate oxide film (5). A method of manufacturing the semiconductor device is provided which attains reduction in gate length without the decrease in driving capability to accomplish the increase in operating speed.

摘要翻译： 半导体器件包括硅衬底（1），一对隔离绝缘膜（9），沟道区（2），一对源/漏区（3），一对氧化硅膜（4），形成在 硅衬底（1）的上表面覆盖在源极/漏极区（3）上，并且栅极结构（8）形成在由硅衬底（1）的上表面限定的第一凹部中，沟道 区域（2）和一对氧化硅膜（4）的侧表面。 栅极结构（8）包括形成在硅衬底（1）的上表面上的栅氧化膜（5），一对氧化硅膜（6），形成在该一对氧化硅的侧表面的下部 以及填充由氧化硅膜（4）的侧面的上部，氧化硅膜（6）和栅极氧化膜（5）所包围的第二凹部的金属膜（7）。 提供了一种制造半导体器件的方法，其在不降低驱动能力的情况下实现栅极长度的减小以实现操作速度的提高。

公开(公告)号：US06235564B1

公开(公告)日：2001-05-22

申请号：US09487620

申请日：2000-01-20

申请人： Yasuyoshi Itoh ,  Yasuo Inoue ,  Hidekazu Oda

发明人： Yasuyoshi Itoh ,  Yasuo Inoue ,  Hidekazu Oda

IPC分类号： H01L21338

CPC分类号： H01L29/66545 ,  H01L21/26586 ,  H01L21/28114 ,  H01L29/1045 ,  H01L29/495 ,  H01L29/6659

摘要： A method of manufacturing a MISFET includes the steps of forming a gate insulation film (2) on a semiconductor substrate (1), forming a dummy gate (3B) made of a material having an etch selectivity relative to the material of the gate insulation film (2) on the gate insulation film (2), implanting an impurity into the semiconductor substrate (1), forming an interlayer insulation film (7), made of a material having an etch selectivity relative to the material of the dummy gate (3B) on a side surface of the dummy gate (3B), etching away the dummy gate (3B), and filling a space in which the dummy gate (3B) has been present with a gate electrode material of metal. Gradually thinning the dummy gate in the step of impurity implantation allows the formation of LDD regions and the patterning of a gate electrode below a minimum patterning size limit of a photolithographic technique. The method eliminates the need to take into consideration an etch selectivity between the gate electrode material and the gate insulation film material to manufacture an all-metal gate electrode.

摘要翻译： 一种制造MISFET的方法包括以下步骤：在半导体衬底（1）上形成栅极绝缘膜（2），形成由相对于栅极绝缘膜的材料具有蚀刻选择性的材料制成的虚拟栅极（3B） （2）在栅极绝缘膜（2）上，将杂质注入到半导体衬底（1）中，形成层间绝缘膜（7），其由具有相对于虚拟栅极（3B）的材料的蚀刻选择性的材料制成 ）在伪栅极（3B）的侧面上，蚀刻掉伪栅极（3B），并且填充其中存在虚拟栅极（3B）的空间与金属栅电极材料。 在杂质注入步骤中使虚拟栅极逐渐变薄，可以形成LDD区域，并使栅电极的图案化成为光刻技术的最小图案化尺寸极限。 该方法消除了考虑栅电极材料和栅极绝缘膜材料之间的蚀刻选择性以制造全金属栅电极的需要。

公开(公告)号：US07960728B2

公开(公告)日：2011-06-14

申请号：US12499209

申请日：2009-07-08

申请人： Yasuyoshi Itoh ,  Yuichi Masutani ,  Eiji Shibata ,  Kenichi Miyamoto

发明人： Yasuyoshi Itoh ,  Yuichi Masutani ,  Eiji Shibata ,  Kenichi Miyamoto

IPC分类号： H01L23/58 ,  H01L29/76 ,  H01L31/00 ,  H01L31/036 ,  H01L31/112

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/66765

摘要： In a method of manufacturing a TFT substrate in accordance with an exemplary aspect of the present invention, an intrinsic semiconductor film, an impurity semiconductor film, and a conductive film for source lines are formed in succession, and a resist having a thin-film portion and a thick-film portions is formed on the conductive film for source lines. Then, etching is performed by using the resist as a mask, and after that, a part of the conductive film for source lines is exposed by removing the thin-film portion of the resist. Next, the exposed conductive film for source lines is etched by using the thick-film portions of the resist a mask, so that the impurity semiconductor film is exposed. Then, by etching the exposed impurity semiconductor film, a back channel region of a TFT 108 is formed. Further, a dummy back channel region 18a, which is irrelevant to the operation of the finished product, is also formed in a portion other than the TFT 108 region.

摘要翻译： 在根据本发明的示例性方面的制造TFT基板的方法中，依次形成本征半导体膜，杂质半导体膜和源极线用导电膜，并且具有薄膜部分的抗蚀剂 并且在用于源极线的导电膜上形成厚膜部分。 然后，通过使用抗蚀剂作为掩模进行蚀刻，之后，通过去除抗蚀剂的薄膜部分来露出用于源极线的导电膜的一部分。 接下来，通过使用抗蚀剂的掩膜的厚膜部分来蚀刻用于源极线的暴露的导电膜，使得杂质半导体膜暴露。 然后，通过蚀刻暴露的杂质半导体膜，形成TFT 108的背沟道区域。 此外，与TFT 108区域以外的部分也形成与成品的操作无关的虚拟背沟道区域18a。

公开(公告)号：US20060030086A1

公开(公告)日：2006-02-09

申请号：US11196574

申请日：2005-08-04

申请人： Yasuyoshi Itoh ,  Takeshi Kubota ,  Toru Takeguchi

发明人： Yasuyoshi Itoh ,  Takeshi Kubota ,  Toru Takeguchi

IPC分类号： H01L21/84 ,  H01L21/425

CPC分类号： H01L29/78621 ,  H01L21/268 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78627

摘要： Impurity ions contained in a semiconductor layer are diffused downwardly from a gate electrode by irradiating laser light from the back surface of a transparent substrate after source-drain regions are formed. Thus, a GOLD structure is formed. Consequently, the GOLD structure is formed by performing a smaller number of processes. Also, variation in characteristics can be suppressed by preventing occurrence of asymmetry between left and right LDD regions.

摘要翻译： 包含在半导体层中的杂质离子通过在形成源极 - 漏极区域之后从透明衬底的背面照射激光而从栅电极向下扩散。 因此，形成GOLD结构。 因此，通过执行较少数量的处理来形成GOLD结构。 此外，通过防止左右LDD区域之间的不对称性可以抑制特性的变化。

公开(公告)号：US20050045880A1

公开(公告)日：2005-03-03

申请号：US10898360

申请日：2004-07-26

申请人： Yasuyoshi Itoh ,  Kaoru Motonami

发明人： Yasuyoshi Itoh ,  Kaoru Motonami

IPC分类号： H01L27/04 ,  H01L21/20 ,  H01L21/322 ,  H01L21/336 ,  H01L21/822 ,  H01L29/786 ,  H01L29/04

CPC分类号： H01L29/66757 ,  H01L29/66765 ,  H01L29/78675 ,  H01L29/78678 ,  Y10S257/913

摘要： A semiconductor device comprises a glass substrate serving as a substrate having an insulated surface and a silicon layer located on a position overlapping with this glass substrate. The silicon layer includes an amorphous gettering region. Preferably, the silicon layer includes a main region serving as an active element region, and the gettering region is preferably included in the remaining portion of the silicon layer excluding the main region. Preferably, the silicon layer may include a portion serving as an active region of a thin-film transistor.

摘要翻译： 半导体器件包括用作具有绝缘表面的基板的玻璃基板和位于与该玻璃基板重叠的位置的硅层。 硅层包括无定形吸气区域。 优选地，硅层包括用作有源元件区域的主区域，并且除了主区域之外的硅层的剩余部分中优选包含吸杂区域。 优选地，硅层可以包括用作薄膜晶体管的有源区的部分。