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    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4060796A

    公开(公告)日：1977-11-29

    申请号：US758447

    申请日：1977-01-11

    申请人： Ryoiku Togei ,  Akira Takei ,  Yoshihiko Hika ,  Kunihiko Wada

    发明人： Ryoiku Togei ,  Akira Takei ,  Yoshihiko Hika ,  Kunihiko Wada

    IPC分类号： G11C11/35 ,  H01L21/3205 ,  H01L27/07 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49 ,  G11C11/40

    CPC分类号： H01L27/0733 ,  G11C11/35 ,  H01L21/32055 ,  H01L27/10805 ,  H01L29/42396 ,  H01L29/4983

    摘要： A semiconductor memory device provided with one transferring electrode, one gate electrode and one diode of a charge coupled device is produced by a process with a reduced number of steps of diffusion and patterning. Both electrodes consists of doped polycrystalline silicon and both are electrically connected to a resistive layer which consists of non-doped polycrystalline silicon. A potential barrier between the region of both electrodes is removed due to the resistive layer. Resistive layer is formed by utilization of a two-stage deposition of the polycrystalline silicon layer with appropriate mashing steps.

    摘要翻译： 设置有电荷耦合器件的一个转移电极，一个栅极电极和一个二极管的半导体存储器件通过具有减少的扩散步骤和图案化步骤的工艺产生。 两个电极由掺杂的多晶硅组成，并且它们都电连接到由非掺杂多晶硅组成的电阻层。 由于电阻层，两个电极的区域之间的势垒被去除。 通过利用适当的糖化步骤的多晶硅层的两级沉积形成电阻层。

    Nonvolatile semiconductor memory device
    4.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US4462089A

    公开(公告)日：1984-07-24

    申请号：US331286

    申请日：1981-12-16

    申请人： Takashi Miida ,  Yoshihiko Hika ,  Akira Takei

    发明人： Takashi Miida ,  Yoshihiko Hika ,  Akira Takei

    IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

    CPC分类号： H01L29/7886 ,  G11C16/0416

    摘要： A nonvolatile semiconductor memory device of a floating-gate type comprises a floating-gate and two control gates. The floating-gate is divided into two conductive regions having a conductivity type opposite to each other. A first control gate is placed above a first region and a second control gate is placed above a second region. In this device, the erase operation is performed by causing avalanche breakdown within the floating-gate.

    摘要翻译： 浮栅型的非易失性半导体存储器件包括浮栅和两个控制栅。 浮栅被分成具有彼此相反的导电类型的两个导电区域。 第一控制栅极位于第一区域的上方，第二控制栅极位于第二区域的上方。 在该装置中，通过使浮栅内的雪崩击穿来进行擦除操作。

    Complementary semiconductor memory device
    5.
    发明授权
    Complementary semiconductor memory device 失效
    互补半导体存储器件

    公开(公告)号：US4330849A

    公开(公告)日：1982-05-18

    申请号：US180805

    申请日：1980-08-27

    申请人： Ryoiku Togei ,  Yoshihiko Hika

    发明人： Ryoiku Togei ,  Yoshihiko Hika

    IPC分类号： G11C11/401 ,  G11C11/403 ,  H01L27/092 ,  H01L27/108 ,  H01L29/78 ,  G11C11/40

    CPC分类号： H01L27/0922 ,  G11C11/403 ,  H01L27/108

    摘要： Disclosed herein is a semiconductor memory device comprising a semiconductor substrate having a first conductivity type, first and second regions of a second conductivity type opposite to said first type formed in the surface of the semiconductor substrate and separated with a certain space therebetween, a third region of the first conductivity type formed in the second region, and a gate electrode formed on an insulating film on the semiconductor substrate between the first and the third regions. By applying a gate voltage to the gate electrode, charge carriers are transferred between the first and second regions in accordance with the data to be stored. The stored data is read out by applying a prescribed gate voltage to the gate electrode and by detecting the value of the current between the third region and the semiconductor substrate.

    摘要翻译： 本文公开了一种半导体存储器件，其包括具有第一导电类型的半导体衬底，第二导电类型的第二和第二区域，形成在半导体衬底的表面中并与之间的一定间隔分隔的第一导电类型的第一导电类型的第三导电类型的第三区域; 形成在第二区域中的第一导电类型的栅极电极和形成在第一和第三区域之间的半导体衬底上的绝缘膜上的栅电极。 通过向栅极施加栅极电压，根据要存储的数据，在第一和第二区域之间传送电荷载流子。 通过向栅电极施加规定的栅极电压并且通过检测第三区域和半导体衬底之间的电流的值来读出存储的数据。