公开(公告)号：US06727571B2

公开(公告)日：2004-04-27

申请号：US10290404

申请日：2002-11-08

申请人： Yuji Sugiyama ,  Yoshiyuki Tonami ,  Masahiko Kawaguchi

发明人： Yuji Sugiyama ,  Yoshiyuki Tonami ,  Masahiko Kawaguchi

IPC分类号： H01L2900

CPC分类号： H01F41/045 ,  H01F17/0006 ,  H01F2017/0073 ,  H01L27/08

摘要： A spiral coil pattern is formed on a substantially rectangular insulation substrate of an inductor by photolithography. In the coil pattern, the electrode width of a portion of the pattern provided in the vicinity of the right short side of the substrate so as to be substantially parallel to the short side is wider than the electrode width of the other portion of the pattern. The interelectrode spacing of a portion of the pattern is wider than the interelectrode spacing of the other portion of the pattern. When the inductance of the inductor is required to be reduced to make the inductance a desired inductance value, the electrode width of the portion of the coil pattern is made wider in the inner direction of the coil pattern than the original electrode width.

摘要翻译： 螺旋线圈图案通过光刻形成在电感器的基本上矩形的绝缘基板上。 在线圈图案中，设置在基板的右短边附近的图案部分的电极宽度大致平行于短边，比图案的另一部分的电极宽度宽。 图案的一部分的电极间距比图案的另一部分的电极间间隔宽。 当需要减小电感器的电感以使电感成为期望的电感值时，线圈图案的部分的电极宽度在线圈图案的内部方向上比原始电极宽度更宽。

公开(公告)号：US20050104218A1

公开(公告)日：2005-05-19

申请号：US10993197

申请日：2004-11-19

申请人： Yoshiyuki Tonami ,  Mitsunori Hatada

发明人： Yoshiyuki Tonami ,  Mitsunori Hatada

IPC分类号： H01L23/12 ,  H01L21/48 ,  H01L23/66 ,  H01P3/08 ,  H01P11/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/16 ,  H05K3/04 ,  H05K3/40 ,  H01L23/495

CPC分类号： H05K3/4061 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/66 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/0306 ,  H05K1/16 ,  H05K1/167 ,  H05K3/048 ,  H05K2201/0317 ,  H05K2203/025 ,  H05K2203/1461 ,  H01L2924/00

摘要： In the production of a high frequency circuit chip in which a wiring pattern is disposed on a substrate having a through-hole, a connecting electrode of the through-hole is formed by filling electrically conductive paste into a perforation and firing it, and the wiring pattern is formed by a lift-off method. Moreover, at least the surface of the substrate for the wiring pattern to be formed thereon is mirror-polished, and thereafter, the wiring pattern is formed on the mirror-polished surface by the lift-off method.

公开(公告)号：US06808641B2

公开(公告)日：2004-10-26

申请号：US09761317

申请日：2001-01-17

申请人： Yoshiyuki Tonami ,  Yoshihiro Koshido

发明人： Yoshiyuki Tonami ,  Yoshihiro Koshido

IPC分类号： H01L2100

CPC分类号： C23F1/02 ,  H01L21/2885 ,  H01L21/76885 ,  H05K3/048 ,  H05K3/108 ,  H05K3/242 ,  H05K3/388 ,  H05K2203/1461

摘要： A method of wiring formation includes forming a feeder film partially on a substrate, forming on the substrate a plating base film via a physical film making method so that the plate base film partially overlaps the feeder film, forming a plated wiring on the plating base film using an electrolytic plating, and selectively removing at least an area of the feeder film which is exposed from the plated wiring, using a wet etching process.

摘要翻译： 布线形成方法包括：在基板上部分地形成供给膜，在基板上通过物理膜的制作方法形成基板，使得基板与基材膜部分重叠，在电镀基膜上形成电镀布线 使用电解电镀，并且使用湿蚀刻工艺选择性地去除从电镀布线暴露的供给膜的至少一个区域。

公开(公告)号：US07316783B2

公开(公告)日：2008-01-08

申请号：US10885306

申请日：2004-07-07

申请人： Yoshiyuki Tonami ,  Yoshihiro Koshido

发明人： Yoshiyuki Tonami ,  Yoshihiro Koshido

IPC分类号： H01L21/00 ,  H01L21/3205 ,  C25D5/00

CPC分类号： C23F1/02 ,  H01L21/2885 ,  H01L21/76885 ,  H05K3/048 ,  H05K3/108 ,  H05K3/242 ,  H05K3/388 ,  H05K2203/1461

摘要： A method of wiring formation includes forming a feeder film partially on a substrate, forming on the substrate a plating base film via a physical film making method so that the plate base film partially overlaps the feeder film, forming a plated wiring on the plating base film using an electrolytic plating, and selectively removing at least an area of the feeder film which is exposed from the plated wiring, using a wet etching process.

摘要翻译： 布线形成方法包括：在基板上部分地形成供给膜，在基板上通过物理膜的制作方法形成基板，使得基板与基材膜部分重叠，在电镀基膜上形成电镀布线 使用电解电镀，并且使用湿蚀刻工艺选择性地去除从电镀布线暴露的供给膜的至少一个区域。

公开(公告)号：US07144618B2

公开(公告)日：2006-12-05

申请号：US10681877

申请日：2003-10-09

申请人： Yoshiyuki Tonami ,  Yuji Sugiyama ,  Michiaki Iha

发明人： Yoshiyuki Tonami ,  Yuji Sugiyama ,  Michiaki Iha

IPC分类号： B32B7/00

CPC分类号： H01L23/49894 ,  H01L21/481 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/4605 ,  H05K3/4667 ,  H05K3/4688 ,  H05K2201/068 ,  Y10T428/24917 ,  Y10T428/24926 ,  H01L2924/00

摘要： A multilayer composite includes an insulating substrate and patterned conductive layers and insulating layers alternately laminated on the insulating substrate. In a laminating process, a correcting insulating layer is formed on a laminate when a predetermined number of layers are laminated or when a predetermined degree of warpage of the laminate is detected by monitoring. The correcting insulating layer has a different composition from that of the other insulating layers to correct the warpage of the laminate.

摘要翻译： 多层复合物包括绝缘基板和交替层压在绝缘基板上的图案化导电层和绝缘层。 在层压工艺中，当层叠有预定数量的层时，或者当通过监测检测到层压体的预定翘曲程度时，在层压板上形成校正绝缘层。 校正绝缘层与其它绝缘层的组成不同，以校正层压体的翘曲。

公开(公告)号：US06838377B2

公开(公告)日：2005-01-04

申请号：US10087915

申请日：2002-03-05

申请人： Yoshiyuki Tonami ,  Mitsunori Hatada

发明人： Yoshiyuki Tonami ,  Mitsunori Hatada

IPC分类号： H01L23/12 ,  H01L21/48 ,  H01L23/66 ,  H01P3/08 ,  H01P11/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/16 ,  H05K3/04 ,  H05K3/40 ,  H01L21/44

CPC分类号： H05K3/4061 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/66 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/0306 ,  H05K1/16 ,  H05K1/167 ,  H05K3/048 ,  H05K2201/0317 ,  H05K2203/025 ,  H05K2203/1461 ,  H01L2924/00

摘要： In the production of a high frequency circuit chip in which a wiring pattern is disposed on a substrate having a through-hole, a connecting electrode of the through-hole is formed by filling electrically conductive paste into a perforation and firing it, and the wiring pattern is formed by a lift-off method. Moreover, at least the surface of the substrate for the wiring pattern to be formed thereon is mirror-polished, and thereafter, the wiring pattern is formed on the mirror-polished surface by the lift-off method.

摘要翻译： 在其中在具有通孔的基板上布置布线图案的高频电路芯片的生产中，通过将导电浆料填充到穿孔中并将其烧结而形成通孔的连接电极，并且布线 图案由剥离法形成。 此外，至少将要形成其上的布线图案的基板的表面进行镜面抛光，然后通过剥离方法在镜面抛光表面上形成布线图案。

公开(公告)号：US5818283A

公开(公告)日：1998-10-06

申请号：US678668

申请日：1996-07-11

申请人： Yoshiyuki Tonami ,  Goro Yoshida ,  Kazuo Yamashita

发明人： Yoshiyuki Tonami ,  Goro Yoshida ,  Kazuo Yamashita

IPC分类号： H03K17/10 ,  H03K17/687 ,  H03K17/693

CPC分类号： H03K17/6874 ,  H03K17/102

摘要： In an FET switch for controllably allowing and inhibiting passage of an input signal in ON state and OFF state, respectively, FETs are connected in a multi-stage configuration. A control voltage adjusting circuit is connected between a gate and one of a drain and a source of each FET. The control voltage adjusting circuit adjusts a gate-source voltage so as to follow the variation of a drain-source voltage. The input voltage applied to the FET switch in OFF state is divided by the plurality of FETs. Since the variation of the gate-source voltage follows the variation of the drain-source voltage, the FET switch is hardly influenced by an amplitude of the input signal.

摘要翻译： 在用于可控制地允许和禁止输入信号在ON状态和OFF状态下的FET开关中，FET分别以多级配置连接。 控制电压调节电路连接在栅极与每个FET的漏极和源极之一之间。 控制电压调节电路调节栅极 - 源极电压以便跟随漏极 - 源极电压的变化。 施加到关断状态的FET开关的输入电压被多个FET分压。 由于栅源电压的变化跟随漏 - 源电压的变化，所以FET开关几乎不受输入信号的幅度的影响。