公开(公告)号：US20170171968A1

公开(公告)日：2017-06-15

申请号：US15039629

申请日：2014-11-24

Applicant: Corning Precision Materials Co., Ltd.

Inventor： Jin Nyoung Heo ,  Tae Hyo Park ,  Dong Keun Shin ,  Jong Taek Kim ,  Sang Yoon Oh ,  Jin Sung Lim

IPC: H05K1/03 ,  H05K3/00 ,  H05K1/09

CPC classification number: H05K1/0393 ,  B32B17/064 ,  G02F1/133305 ,  H05K1/0224 ,  H05K1/0306 ,  H05K1/0353 ,  H05K1/09 ,  H05K1/095 ,  H05K1/097 ,  H05K3/0067 ,  H05K3/12 ,  H05K3/1216 ,  H05K3/16 ,  H05K2201/026 ,  H05K2201/0317 ,  H05K2201/0326 ,  H05K2203/0113 ,  H05K2203/1545

Abstract: The present invention relates to a flexible hybrid substrate for a display and a method for manufacturing the same and, more specifically, to a flexible hybrid substrate for a display, which has a reduced occurrence of cracks, an improved level of flexibility, and can be used in a high-temperature process for manufacturing a display element, and a method for manufacturing the same. To this end, the present invention provides a flexible hybrid substrate for a display and a method for manufacturing the same, the flexible hybrid substrate for a display comprising: an ultra-thin plate glass; a first transparent thin film formed on one surface of the ultra-thin plate glass; and a second transparent thin film formed on the other surface of the ultra-thin plate glass, wherein the second transparent thin film includes a transparent conductive polymer.

公开(公告)号：US09543128B2

公开(公告)日：2017-01-10

申请号：US14090203

申请日：2013-11-26

Applicant: MITSUBISHI MATERIALS CORPORATION

Inventor： Satoru Mori ,  Souhei Nonaka

IPC: B32B15/20 ,  H01J37/34 ,  H05K3/02 ,  H05K1/09 ,  H05K3/06

CPC classification number: H01J37/3426 ,  H05K1/09 ,  H05K3/022 ,  H05K3/06 ,  H05K2201/0317 ,  H05K2201/0338 ,  Y10T428/1291

Abstract: A sputtering target for forming protective film according to the invention is used to form protective film on one surface or both surfaces of a Cu wiring film, and includes 8.0 to 11.0% by mass of Al, 3.0 to 5.0% by mass of Fe, 0.5 to 2.0% by mass of Ni and 0.5 to 2.0% by mass of Mn with a remainder of Cu and inevitable impurities. In addition, a laminated wiring film includes a Cu wiring film and protective film formed on one surface or both surfaces of the Cu wiring film, and the protective film is formed by using the above sputtering target.

Abstract translation: 根据本发明的用于形成保护膜的溅射靶用于在Cu布线膜的一个表面或两个表面上形成保护膜，并且包括8.0至11.0质量％的Al，3.0至5.0质量％的Fe，0.5 至2.0质量％的Ni和0.5〜2.0质量％的Mn，余量为Cu和不可避免的杂质。 此外，层叠布线膜包括Cu布线膜和形成在Cu布线膜的一个表面或两个表面上的保护膜，并且通过使用上述溅射靶形成保护膜。

公开(公告)号：US20160338192A1

公开(公告)日：2016-11-17

申请号：US15222333

申请日：2016-07-28

Applicant: Stephen GONYA ,  James Sean EICHE ,  James PATTERSON ,  Kenneth R. TWIGG

Inventor： Stephen GONYA ,  James Sean EICHE ,  James PATTERSON ,  Kenneth R. TWIGG

IPC: H05K1/02 ,  H05K3/06

CPC classification number: H05K1/0284 ,  H05K3/06 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09872

Abstract: A method of producing a non-planar conforming circuit on a non-planar surface includes creating a first set of conforming layers. The first set of conforming layers is created by applying an oxide dielectric layer to the surface, applying a conductive material layer to the oxide dielectric layer, applying a resist layer to the conductive material layer, patterning the resist layer according to a desired circuit layout, etching the surface to remove exposed conductive material, and stripping the resist layer. The process may be repeated to form multiple layers of conforming circuits with electrical connections between layers formed by blind microvias. The resulting set of conforming layers can be sealed.

Abstract translation: 在非平面表面上制造非平面符合电路的方法包括产生第一组一致的层。 通过向表面施加氧化物电介质层，向氧化物介电层施加导电材料层，向导电材料层施加抗蚀剂层，根据期望的电路布局图案化抗蚀剂层，形成第一组一致性层， 蚀刻表面以除去暴露的导电材料，并剥离抗蚀剂层。 该过程可以重复以形成具有通过盲微孔形成的层之间的电连接的多层符合电路。 所得到的一组适形层可以被密封。

公开(公告)号：US20160278205A1

公开(公告)日：2016-09-22

申请号：US14371387

申请日：2014-03-07

Applicant: LG CHEM, LTD.

Inventor： Sung-Hak BAE ,  Sang-Choll HAN ,  Byong-Mook KIM

IPC: H05K1/02 ,  H05K3/14 ,  H05K1/03 ,  H05K3/38 ,  H05K1/09 ,  H05K3/04 ,  H05K3/00

CPC classification number: H05K1/0296 ,  G03F7/00 ,  H05B3/12 ,  H05B3/84 ,  H05B2203/017 ,  H05K1/0274 ,  H05K1/0313 ,  H05K1/09 ,  H05K3/0023 ,  H05K3/0044 ,  H05K3/04 ,  H05K3/045 ,  H05K3/146 ,  H05K3/38 ,  H05K2201/0108 ,  H05K2201/0129 ,  H05K2201/0317 ,  H05K2201/09036 ,  H05K2203/0108

Abstract: The present disclosure relates to a transparent substrate including: a resin pattern layer including a plurality of grooves respectively including side surfaces and a bottom surface; and, a conductive layer formed within the grooves, wherein a line width of the conductive layer is 0.1 μm to 3 μm and an average height of the conductive layer is 5% to 50% of a maximum depth of each of the grooves, and a manufacturing method thereof, such that simplicity in a manufacturing process and a consecutive process are enabled, manufacturing costs are inexpensive, and a transparent substrate having superior electrical conductivity and transparency characteristics is manufactured.

Abstract translation: 本公开涉及一种透明基板，包括：树脂图案层，其包括分别包括侧表面和底表面的多个凹槽; 以及形成在所述沟槽内的导电层，其中所述导电层的线宽为0.1μm〜3μm，所述导电层的平均高度为每个所述槽的最大深度的5％〜50％，a 使制造工艺和连续工序简单化，制造成本便宜，制造出具有优异的导电性和透明性的透明基板。

公开(公告)号：US20160278202A1

公开(公告)日：2016-09-22

申请号：US14978709

申请日：2015-12-22

Applicant: SAE MAGNETICS (H.K.) LTD.

Inventor： Akio NAKAO

IPC: H05K1/02 ,  H05K3/30 ,  H05K1/18

CPC classification number: H05K3/284 ,  H01L21/561 ,  H01L21/568 ,  H01L23/552 ,  H01L24/97 ,  H01L2924/15159 ,  H01L2924/15313 ,  H05K1/0218 ,  H05K3/0097 ,  H05K2201/0317 ,  H05K2201/0715 ,  H05K2201/09145 ,  H05K2201/09845

Abstract: An electronic component module includes a substrate; at least one electronic component mounted on an electronic component mounting surface of the substrate; an insulating body covering the electronic component on the electronic component mounting surface of the substrate; and a metal film formed by sputtering, the metal film covering at least one exterior surface of the insulating body and at least one side surface of the substrate. The substrate has a recess portion formed on a periphery of the surface of the substrate that is opposite to the electronic component mounting surface, and the recess portion has a top surface parallel to the electronic component mounting surface and a side surface perpendicular to the top surface, and the metal film is extended to cover the top surface of the recess portion, without covering the side surface thereof. It obtains improved electromagnetic wave shielding effect and improved manufacturing efficiency.

Abstract translation: 电子部件模块包括基板; 安装在所述基板的电子部件安装表面上的至少一个电子部件; 覆盖基板的电子部件安装面上的电子部件的绝缘体; 以及通过溅射形成的金属膜，所述金属膜覆盖所述绝缘体的至少一个外表面和所述基板的至少一个侧表面。 基板具有形成在基板表面的与电子部件安装面相反的周边的凹部，凹部具有平行于电子部件安装面的上表面和与顶面垂直的侧面 并且金属膜延伸以覆盖凹部的顶表面而不覆盖其侧表面。 获得改进的电磁波屏蔽效果，提高制造效率。

公开(公告)号：US20160105970A1

公开(公告)日：2016-04-14

申请号：US14511549

申请日：2014-10-10

Applicant: Lockheed Martin Corporation

Inventor： Stephen Gonya ,  James Sean Eiche ,  James Patterson ,  Kenneth R. Twigg

IPC: H05K3/02 ,  H05K3/28 ,  H05K1/11 ,  H05K1/02 ,  H05K1/09 ,  H05K3/00 ,  H05K3/40

CPC classification number: H05K1/0284 ,  H05K3/06 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09872

Abstract: A method of producing a non-planar conforming circuit on a non-planar surface includes creating a first set of conforming layers. The first set of conforming layers is created by applying an oxide dielectric layer to the surface, applying a conductive material layer to the oxide dielectric layer, applying a resist layer to the conductive material layer, patterning the resist layer according to a desired circuit layout, etching the surface to remove exposed conductive material, and stripping the resist layer. The process may be repeated to form multiple layers of conforming circuits with electrical connections between layers formed by blind microvias. The resulting set of conforming layers can be sealed.

公开(公告)号：US09288891B2

公开(公告)日：2016-03-15

申请号：US14387145

申请日：2013-03-08

Applicant: Sony Corporation

Inventor： Kazuya Hayashibe ,  Hiroshi Tazawa ,  Shunichi Kajiya

IPC: H05K1/03 ,  H05K1/09 ,  C23C26/00 ,  H05K1/02 ,  G06F3/041 ,  G09F9/00 ,  H05B33/14 ,  H05K3/00 ,  H05K3/06 ,  H05K3/02 ,  H05K3/38

CPC classification number: H05K1/02 ,  G06F3/041 ,  G09F9/00 ,  H05B33/14 ,  H05K1/0306 ,  H05K3/0014 ,  H05K3/02 ,  H05K3/06 ,  H05K3/389 ,  H05K2201/0317 ,  H05K2201/0326 ,  H05K2201/09027 ,  H05K2203/0108 ,  H05K2203/0143 ,  H05K2203/0537 ,  H05K2203/10

Abstract: A conductive element includes: a substrate having a first wavy surface, a second wavy surface, and a third wavy surface; a first layer provided on the first wavy surface; and a second layer formed on the second wavy surface. The first and second layers form a conductive pattern portion. The first, second, and third wavy surfaces satisfy the following relationship: 0≦(Am1/λm1)

Abstract translation: 导电元件包括​​：具有第一波状表面，第二波浪表面和第三波浪表面的基板; 设置在第一波浪面上的第一层; 以及形成在第二波浪表面上的第二层。 第一和第二层形成导电图案部分。 第一，第二和第三波形表面满足以下关系：0＆nlE;（Am1 /λm1）<（Am2 /λm2）<（Am3 /λm3）＆nlE; 1.8（其中Am1是第一波形表面的振动的平均宽度 Am2是第二波形表面的平均振动幅度，Am3是第三波形表面的平均振动幅度，λm1是第一波状表面的平均波长，λm2是第二波状表面的平均波长， λm3是第三波形表面的平均波长）

公开(公告)号：US20160044778A1

公开(公告)日：2016-02-11

申请号：US14780529

申请日：2014-03-03

Applicant: KANEKA CORPORATION

Inventor： Tooru Irie ,  Takahisa Fujimoto ,  Takashi Kuchiyama ,  Hironori Hayakawa ,  Shinya Omoto ,  Kenji Yamamoto

IPC: H05K1/02 ,  H05K3/22 ,  H05K3/06 ,  H05K3/00 ,  H05K1/03 ,  H05K1/09

CPC classification number: H05K1/0274 ,  G06F3/044 ,  G06F2203/04103 ,  G06F2203/04112 ,  H05K1/0296 ,  H05K1/0326 ,  H05K1/09 ,  H05K3/0064 ,  H05K3/06 ,  H05K3/067 ,  H05K3/108 ,  H05K3/227 ,  H05K3/388 ,  H05K2201/0108 ,  H05K2201/0145 ,  H05K2201/0317 ,  H05K2201/09663 ,  H05K2201/0979

Abstract: Provided is a transparent conductive film including a transparent electrode layer composed of a patterned thin metal wire on at least one surface of a transparent film substrate. The line width of the wire is 5 μm or less. The wire includes a first metal layer and a second metal layer that is in contact with the first metal layer, in this order from a transparent film substrate side. Both of the first and second metal layers contain copper in an amount of 90% by weight or more. The total film thickness of the first and second metal layers is 150 to 1000 nm. The diffraction angle 2θ of the (111) plane of the second metal layer is less than 43.400° as measured using a CuKα ray as an X-ray source, and the first metal layer has crystal properties different from those of the second metal layer.

Abstract translation: 提供一种透明导电膜，其包括在透明膜基板的至少一个表面上由图案化的金属细线构成的透明电极层。 线的线宽为5μm以下。 导线包括从透明膜基板一侧依次与第一金属层接触的第一金属层和第二金属层。 第一和第二金属层都含有90重量％以上的铜。 第一和第二金属层的总膜厚度为150〜1000nm。 衍射角2＆thetas; 使用CuKα射线作为X射线源测定的第二金属层的（111）面的面积小于43.400°，第一金属层的结晶特性与第二金属层的晶体性质不同。

公开(公告)号：US09155188B2

公开(公告)日：2015-10-06

申请号：US13631156

申请日：2012-09-28

Applicant: Apple Inc.

Inventor： Nicholas G. Merz ,  Hong Wang ,  Michael M. Nikkhoo ,  Dennis R. Pyper ,  Christopher Matthew Werner

IPC: H05K9/00 ,  H05K1/02 ,  H05K3/28

CPC classification number: H05K1/0218 ,  H05K3/284 ,  H05K2201/0317 ,  H05K2201/09618 ,  H05K2201/09872 ,  H05K2201/09909 ,  H05K2201/10371 ,  H05K2201/2018 ,  Y10T29/4913 ,  Y10T29/49146

Abstract: Methods and apparatuses are disclosed for fabricating a printed circuit board (PCB) having electromagnetic interference (EMI) shielding and also having reduced volume over conventional frame-and-shield approaches. Some embodiments include fabricating the PCB by mounting an integrated circuit to the PCB, outlining an area corresponding to the integrated circuit with a number of grounded vias, selectively applying an insulating layer over the PCB such that at least one of the grounded vias are exposed, and selectively applying a conductive layer over the PCB such that the conductive layer covers at least a portion of the integrated circuit and such that the conductive layer is coupled to the at least one of the grounded vias that are exposed.

Abstract translation: 公开了用于制造具有电磁干扰（EMI）屏蔽的印刷电路板（PCB）的方法和装置，并且与传统的框架 - 屏蔽方法相比也具有减小的体积。 一些实施例包括通过将集成电路安装到PCB来制造PCB，通过多个接地通孔来概括对应于集成电路的区域，在PCB上选择性地施加绝缘层，使得接地通孔中的至少一个暴露， 以及选择性地在所述PCB上施加导电层，使得所述导电层覆盖所述集成电路的至少一部分，并且使得所述导电层耦合到暴露的所述接地通孔中的至少一个。

公开(公告)号：US20150230343A1

公开(公告)日：2015-08-13

申请号：US14693159

申请日：2015-04-22

Applicant: ULVAC, Inc.

Inventor： Satoru TAKASAWA ,  Shuhei ICHIKAWA ,  Isao SUGIURA ,  Satoru ISHIBASHI ,  Junichi NITTA

IPC: H05K3/16 ,  H05K1/11 ,  H05K3/18 ,  H05K1/03 ,  C23F1/02 ,  H05K3/06

CPC classification number: H05K3/16 ,  C22C9/01 ,  C22C9/06 ,  C23C14/205 ,  C23C14/3414 ,  C23F1/02 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0366 ,  H05K1/115 ,  H05K3/06 ,  H05K3/108 ,  H05K3/188 ,  H05K3/388 ,  H05K3/4644 ,  H05K2201/0209 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09563 ,  H01L2224/0401

Abstract: A mounting device in which a conductive film that is not separated is formed on a resin substrate. Alloy thin films, which contain more than 50% by atom of Cu, 5% by atom or more and 30% by atom or less of Ni, and 3% by atom or more and 10% by atom or less of Al, are formed on a base consisting of a resin so as to be brought into contact with a surface of the base by sputtering. Conductive films consisting of copper are formed on surfaces of the alloy thin films so as to obtain a wiring film having a two-layer structure and a metal plug filled in a connection hole. The alloy thin films have high adhesion to a resin; and hence, the wiring film and the metal plug are not separated.

Abstract translation: 在树脂基板上形成没有分离的导电膜的安装装置。 含有超过50原子％的Cu，5原子％以上，30原子％以下的Ni，3原子％以上10原子以下的Al的合金薄膜形成为 在由树脂构成的基底上，通过溅射与基底的表面接触。 在合金薄膜的表面上形成由铜组成的导电膜，以获得具有两层结构的布线膜和填充在连接孔中的金属塞。 合金薄膜对树脂的粘附性高; 因此，布线膜和金属插塞不分离。