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公开(公告)号：US20120054469A1
公开(公告)日：2012-03-01
申请号：US13209994
申请日：2011-08-15
CPC分类号： G06F15/7803
摘要： A blade server apparatus including a plurality of server modules, a backplane for mounting the plurality of server modules thereon, and an SMP coupling device having wiring lines to SMP couple the plurality of server modules. Each of the server modules has one or more processors controlled by firmware and a module manager for managing its own server module, the module manager has an ID determiner for informing each processor of a processor ID, each processor has a processing unit and an SMP virtual connecting unit for instructing ones of wiring lines of the SMP coupling device through which a packet received from the processing unit is to be transmitted, and an ID converter for converting the processor ID and informing it to the virtual connecting unit is provided within the firmware.
摘要翻译： 一种刀片服务器装置，包括多个服务器模块，用于在其上安装多个服务器模块的背板以及具有连接到多个服务器模块的SMP的布线的SMP耦合装置。 每个服务器模块具有由固件控制的一个或多个处理器和用于管理其自己的服务器模块的模块管理器，模块管理器具有用于向每个处理器通知处理器ID的ID确定器，每个处理器具有处理单元和SMP虚拟 连接单元，用于指示要从所述处理单元接收到的分组的所述SMP耦合设备的布线的哪个布线，以及用于将所述处理器ID转换并通知所述虚拟连接单元的ID转换器设置在所述固件内。
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公开(公告)号：US08745275B2
公开(公告)日：2014-06-03
申请号：US13209994
申请日：2011-08-15
IPC分类号： G06F3/00
CPC分类号： G06F15/7803
摘要： A blade server apparatus including a plurality of server modules, a backplane for mounting the plurality of server modules thereon, and an SMP coupling device having wiring lines to SMP couple the plurality of server modules. Each of the server modules has one or more processors controlled by firmware and a module manager for managing its own server module, the module manager has an ID determiner for informing each processor of a processor ID, each processor has a processing unit and an SMP virtual connecting unit for instructing ones of wiring lines of the SMP coupling device through which a packet received from the processing unit is to be transmitted, and an ID converter for converting the processor ID and informing it to the SMP virtual connecting unit is provided within the firmware.
摘要翻译： 一种刀片服务器装置，包括多个服务器模块，用于在其上安装多个服务器模块的背板以及具有连接到多个服务器模块的SMP的布线的SMP耦合装置。 每个服务器模块具有由固件控制的一个或多个处理器和用于管理其自己的服务器模块的模块管理器，模块管理器具有用于向每个处理器通知处理器ID的ID确定器，每个处理器具有处理单元和SMP虚拟 连接单元，用于指示要发送从处理单元接收到的分组的SMP耦合设备的布线，以及用于将处理器ID转换并通知给SMP虚拟连接单元的ID转换器设置在固件内 。
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公开(公告)号：US09024196B2
公开(公告)日：2015-05-05
申请号：US12985765
申请日：2011-01-06
CPC分类号： H05K1/0248 , H05K1/0245 , H05K1/025 , H05K2201/09263 , H05K2201/09727
摘要： There is provided a printed circuit board having a differential signal transmission line composed of non-skew-adjusting portions and skew-adjusting portions. The non-skew-adjusting portion consists of parallel conductive traces spaced apart by a spacing. The skew-adjusting portion consists of a pair of meander traces for the skew adjustment. The skew-adjusting portion include convex transmission line segments and concave transmission line segments. The convex transmission line segment has parallel traces having a differential trace pair spacing greater than the differential trace pair spacing in the non-skew-adjusting portion. The concave transmission line segment has parallel traces having a differential trace pair spacing smaller than the differential trace pair spacing in the non-skew-adjusting portion.
摘要翻译： 提供一种印刷电路板，其具有由非偏斜调整部分和偏斜调节部分组成的差分信号传输线。 非偏斜调节部分由间隔开的平行导电迹线组成。 偏斜调节部分由一对弯曲迹线组成，用于偏斜调整。 偏斜调整部分包括凸传输线段和凹传输线段。 凸形传输线段具有平行迹线，其具有大于非偏斜调整部分中的差分迹线对间隔的差分迹线对间隔。 凹形传输线段具有在非偏斜调节部分中具有小于差分迹线对间隔的差分迹线对间隔的平行迹线。
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公开(公告)号：US5576997A
公开(公告)日：1996-11-19
申请号：US309418
申请日：1994-09-20
申请人： Noboru Masuda , Kazunori Nakajima , Hideo Maejima
发明人： Noboru Masuda , Kazunori Nakajima , Hideo Maejima
CPC分类号： G11C7/1048 , G11C5/063
摘要： A data processing system having a logic LSI, a plurality of memory LSIs and a circuit which eliminates delays in the time at which data read out form the memory LSIs reach the logic LSI. The circuit includes variable delay circuits for delaying the data signals read out of the memory LSIs. A control circuit start monitors the time when the data read out of the individual memory LSIs arrive at flip-flops which output the data to the logic LSI. The delay times in the variable delay circuits are controlled by the control circuit for the individual memory LSIs so that the times the data read out from the memory LSIs reach the logic LSI may coincide with a predetermined standard time. Thus, the read data from the individual memory LSIs are caused to reach the flip-flops simultaneously.
摘要翻译： 具有逻辑LSI，多个存储器LSI的数据处理系统和消除从存储器LSI读出的数据到达逻辑LSI的时间的延迟的电路。 电路包括用于延迟从存储器LSI读出的数据信号的可变延迟电路。 控制电路开始监视从个别存储器LSI读出的数据到达将数据输出到逻辑LSI的触发器的时间。 可变延迟电路中的延迟时间由各个存储器LSI的控制电路控制，使得从存储器LSI读出的数据达到逻辑LSI的时间可以与预定的标准时间一致。 因此，来自各个存储器LSI的读取数据被同时到达触发器。
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5.发明授权Electronic circuit structure, power supply apparatus, power supply system, and electronic apparatus 有权电子电路结构，电源装置，供电系统和电子设备公开(公告)号：US07911769B2
公开(公告)日：2011-03-22
申请号：US12487279
申请日：2009-06-18
申请人： Hideho Yamamura , Naoki Maru , Kazunori Nakajima , Koji Nisisu , Shigeo Oomae
发明人： Hideho Yamamura , Naoki Maru , Kazunori Nakajima , Koji Nisisu , Shigeo Oomae
IPC分类号： H02B1/20
CPC分类号： H05K1/0263 , H05K2201/10272
摘要： This invention prevents a deterioration of efficiency of a power supply apparatus due to a semiconductor power supply voltage drop, prevents an increase in wasted power, and prevents erroneous operations due to feeder wire voltage drop. In the mounting structure of electronic circuits having a plurality of busbars as current paths on a printed circuit board, the plurality of busbars have almost parallel portions spaced a predetermined distance apart; a span of the parallel portions of the plurality of busbars is greater than the predetermined distance; and in the parallel portions of the plurality of busbars, the plurality of busbars are connected by a wiring pattern. In the switching power supply apparatus built on a printed circuit board, with its output voltage of less than 2 V and its output current of more than 100 A, a means is provided for making the power efficiency higher than 70%.
摘要翻译： 本发明可防止由于半导体电源电压下降导致的电源装置的效率的劣化，防止浪费电力的增加，并且防止由于馈线电压下降引起的错误操作。 在具有作为印刷电路板上的电流路径的多个母线的电子电路的安装结构中，多个母线具有间隔开预定距离的几乎平行的部分; 多个汇流条的平行部分的跨度大于预定距离; 并且在多个母线的平行部分中，多个母线通过布线图案连接。 在内置于印刷电路板上的开关电源装置中，其输出电压小于2V，其输出电流大于100A，提供了使功率效率高于70％的装置。
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公开(公告)号：US5729550A
公开(公告)日：1998-03-17
申请号：US618787
申请日：1996-03-20
申请人： Kazunori Nakajima , Noboru Masuda , Tadaaki Isobe , Masamori Kashiyama , Bunichi Fujita , Masakazu Yamamoto
发明人： Kazunori Nakajima , Noboru Masuda , Tadaaki Isobe , Masamori Kashiyama , Bunichi Fujita , Masakazu Yamamoto
CPC分类号： G06F5/06
摘要： In transmitting and receiving signals between a plurality of units in a information processing system, signals can be transmitted and received between circuits operated by asynchronous clocks which are the same in period (frequency) but not necessarily to be the same in phase, thereby permitting the information processing system to operate with a shorter clock period. A delay circuit arranged in the communication path is so controllable that the data sent out in synchronism with the clock signal of a transmitting unit is correctly retrieved in synchronism with the clock signal of a receiving unit. Further, data having a predetermined simple pattern is sent out in synchronism with the clock signal of the transmitting unit, and it is decided whether the data has been correctly received by the receiving unit. The delay circuit is automatically controlled by use of the result of decision.
摘要翻译： 在信息处理系统中的多个单元之间发送和接收信号时，可以在由周期（频率）相同但不一定相位的异步时钟操作的电路之间发送和接收信号，从而允许 信息处理系统在较短的时钟周期内运行。 布置在通信路径中的延迟电路是可控的，使得与发送单元的时钟信号同步发送的数据与接收单元的时钟信号同步正确检索。 此外，与发送单元的时钟信号同步地发送具有预定简单模式的数据，并且确定数据是否已被接收单元正确地接收。 延迟电路由决定结果自动控制。
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公开(公告)号：US5926766A
公开(公告)日：1999-07-20
申请号：US559468
申请日：1995-11-15
申请人： Masato Yamagata , Kazunori Nakajima
发明人： Masato Yamagata , Kazunori Nakajima
CPC分类号： H04M1/72511 , H04M1/72505 , H04W16/06 , H04W52/0274 , H04W88/021
摘要： In a cordless telephone having no control channel, the time required for connecting a cordless handset to a base unit is reduced in a cordless telephone wherein a cordless handset and a base unit are connected using any one of a plurality of communication channels to allow a call, the plurality of communication channels are divided into a plurality of groups. By using a communication channel included in one of the plurality of groups, standby, calling, and call receiving modes of operation are effected.
摘要翻译： 在没有控制信道的无绳电话中，在无绳电话中减少了将无绳手机连接到基站单元所需的时间，其中使用多个通信信道中的任何一个来连接无绳手机和基站单元以允许呼叫 ，将多个通信信道分成多个组。 通过使用包括在多个组中的一个组中的通信信道，实现备用，呼叫和呼叫接收操作模式。
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公开(公告)号：US5822329A
公开(公告)日：1998-10-13
申请号：US949783
申请日：1997-10-14
申请人： Kazunori Nakajima , Noboru Masuda , Tadaaki Isobe , Masamori Kashiyama , Bunichi Fujita , Masakazu Yamamoto
发明人： Kazunori Nakajima , Noboru Masuda , Tadaaki Isobe , Masamori Kashiyama , Bunichi Fujita , Masakazu Yamamoto
CPC分类号： G06F5/06
摘要： In transmitting and receiving signals between a plurality of units in a information processing system, signals can be transmitted and received between circuits operated by asynchronous clocks which are the same in period (frequency) but not necessarily to be the same in phase, thereby permitting the information processing system to operate with a shorter clock period. A delay circuit arranged in the communication path is so controllable that the data sent out in synchronism with the clock signal of a transmitting unit is correctly retrieved in synchronism with the clock signal of a receiving unit. Further, data having a predetermined simple pattern is sent out in synchronism with the clock signal of the transmitting unit, and it is decided whether the data has been correctly received by the receiving unit. The delay circuit is automatically controlled by use of the result of decision.
摘要翻译： 在信息处理系统中的多个单元之间的发送和接收信号中，可以在由周期（频率）相同但不必相同的异步时钟操作的电路之间发送和接收信号，从而允许 信息处理系统在较短的时钟周期内运行。 布置在通信路径中的延迟电路是可控的，使得与发送单元的时钟信号同步发送的数据与接收单元的时钟信号同步正确检索。 此外，与发送单元的时钟信号同步地发送具有预定简单模式的数据，并且确定数据是否已被接收单元正确地接收。 延迟电路由决定结果自动控制。
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公开(公告)号：US5654651A
公开(公告)日：1997-08-05
申请号：US544730
申请日：1995-10-18
IPC分类号： H03K19/0948 , H03K19/20
CPC分类号： H03K19/0948
摘要： A static logic circuit employs pull-down type logic gates having logic transistors forming a power supply current path and logic transistors forming a grounding current path and having current drive abilities higher than those of the logic transistors forming the power supply current path, and pull-up type logic gates having logic transistors forming a power supply current path and logic transistors forming a grounding current path and having current drive abilities lower than the logic transistors forming the power supply current path, and comprises logic series formed by alternately cascading the two types of the logic gates. The static logic circuit is provided with signal merged logic circuits each of which provides a signal having a high speed falling transient and a high speed rising transient by merging the output signals of the logic series.
摘要翻译： 静态逻辑电路采用具有形成电源电流路径的逻辑晶体管和形成接地电流路径的逻辑晶体管并具有高于形成电源电流通路的逻辑晶体管的电流驱动能力的下拉型逻辑门， 具有形成电源电流路径的逻辑晶体管和形成接地电流路径的逻辑晶体管，并且具有低于形成电源电流路径的逻辑晶体管的电流驱动能力的逻辑门，并且包括通过交替级联两种类型 逻辑门。 静态逻辑电路设置有信号合并逻辑电路，每个逻辑电路通过合并逻辑系列的输出信号来提供具有高速下降瞬变和高速上升瞬变的信号。
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10.发明授权Electronic circuit structure, power supply apparatus, power supply system, and electronic apparatus 失效电子电路结构，电源装置，供电系统和电子设备公开(公告)号：US07548411B2
公开(公告)日：2009-06-16
申请号：US11260210
申请日：2005-10-28
申请人： Hideho Yamamura , Naoki Maru , Kazunori Nakajima , Koji Nisisu , Shigeo Oomae
发明人： Hideho Yamamura , Naoki Maru , Kazunori Nakajima , Koji Nisisu , Shigeo Oomae
IPC分类号： H02B1/20
CPC分类号： H05K1/0263 , H05K2201/10272
摘要： This invention prevents a deterioration of efficiency of a power supply apparatus due to a semiconductor power supply voltage drop, prevents an increase in wasted power, and prevents erroneous operations due to feeder wire voltage drop.In the mounting structure of electronic circuits having a plurality of busbars as current paths on a printed circuit board, the plurality of busbars have almost parallel portions spaced a predetermined distance apart; a span of the parallel portions of the plurality of busbars is greater than the predetermined distance; and in the parallel portions of the plurality of busbars, the plurality of busbars are connected by a wiring pattern. In the switching power supply apparatus built on a printed circuit board, with its output voltage of less than 2 V and its output current of more than 100 A, a means is provided for making the power efficiency higher than 70%.
摘要翻译： 本发明可防止由于半导体电源电压下降导致的电源装置的效率的劣化，防止浪费电力的增加，并且防止由于馈线电压下降引起的错误操作。 在具有作为印刷电路板上的电流路径的多个母线的电子电路的安装结构中，多个母线具有间隔开预定距离的几乎平行的部分; 多个汇流条的平行部分的跨度大于预定距离; 并且在多个母线的平行部分中，多个母线通过布线图案连接。 在内置于印刷电路板上的开关电源装置中，其输出电压小于2V，其输出电流大于100A，提供了使功率效率高于70％的装置。
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