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    Method for calibrating a time-to-digital converter system and time-to-digital converter system
    1.
    发明授权
    Method for calibrating a time-to-digital converter system and time-to-digital converter system 有权

    公开(公告)号：US10732576B2

    公开(公告)日：2020-08-04

    申请号：US16477265

    申请日：2017-12-08

    Applicant: ams AG

    Inventor： Christian Mautner ,  Kerry Glover ,  Friedrich Bahnmueller

    IPC: G04F10/00

    Abstract: A time-to-digital converter system has at least one time-to-digital converter comprising an oscillator, a counter being driven by the oscillator, an evaluation block connected to the counter and configured for determining a time difference associated with a start signal and a stop signal, and a histogram block with a number of bins for recording entries associated with the time difference. The system can be calibrated by operating or preparing to operate the time-to-digital converter system with a measurement clock signal defining a measurement interval, providing a calibration clock signal having a frequency higher than the measurement clock signal by a predefined ratio, using a selected clock edge of the calibration clock signal as the start signal and a subsequent clock edge of the calibration clock signal as the stop signal. The evaluation block determines a calibration time difference based on the respective clock edges of the calibration clock signal used as the start signal and the stop signal. A time measure associated with a counter step of the counter is determined based on the predefined ratio and the calibration time difference.

    TIME-OF-FLIGHT ARRANGEMENT AND METHOD FOR A TIME-OF-FLIGHT MEASUREMENT
    2.
    发明申请
    TIME-OF-FLIGHT ARRANGEMENT AND METHOD FOR A TIME-OF-FLIGHT MEASUREMENT 审中-公开

    公开(公告)号：US20200379095A1

    公开(公告)日：2020-12-03

    申请号：US16963329

    申请日：2019-01-30

    Applicant: ams AG

    Inventor： Robert Kappel ,  Christian Mautner

    IPC: G01S7/4865 ,  G01S7/484 ,  G01S7/497

    Abstract: A time-of-flight arrangement (10) comprises a laser (15), a laser driver (12), a clock generator (11) that is coupled to the laser (15) via the laser driver (12), a photodiode circuit (50) and a time-to-digital converter (14). The photodiode circuit (50) comprises an avalanche photodiode (51), a quenching circuit (52), a diode node (53) and a readout circuit (54). The quenching circuit (52) is coupled via the diode node (53) to the avalanche photodiode (51). An input of the readout circuit (54) is connected to the diode node (53). At least one of the clock generator (11) and the readout circuit (54) is coupled on its output side to the input side of the time-to-digital converter (14).

    METHOD FOR CALIBRATING A TIME-TO-DIGITAL CONVERTER SYSTEM AND TIME-TO-DIGITAL CONVERTER SYSTEM
    3.
    发明申请
    METHOD FOR CALIBRATING A TIME-TO-DIGITAL CONVERTER SYSTEM AND TIME-TO-DIGITAL CONVERTER SYSTEM 审中-公开

    公开(公告)号：US20190361404A1

    公开(公告)日：2019-11-28

    申请号：US16477265

    申请日：2017-12-08

    Applicant: ams AG

    Inventor： Christian Mautner ,  Kerry Glover ,  Friedrich Bahnmueller

    IPC: G04F10/00

    Abstract: A time-to-digital converter system has at least one time-to-digital converter comprising an oscillator, a counter being driven by the oscillator, an evaluation block connected to the counter and configured for determining a time difference associated with a start signal and a stop signal, and a histogram block with a number of bins for recording entries associated with the time difference. The system can be calibrated by operating or preparing to operate the time-to-digital converter system with a measurement clock signal defining a measurement interval, providing a calibration clock signal having a frequency higher than the measurement clock signal by a predefined ratio, using a selected clock edge of the calibration clock signal as the start signal and a subsequent clock edge of the calibration clock signal as the stop signal. The evaluation block determines a calibration time difference based on the respective clock edges of the calibration clock signal used as the start signal and the stop signal. A time measure associated with a counter step of the counter is determined based on the predefined ratio and the calibration time difference.

    METHOD FOR CALIBRATING A TIME-OF-FLIGHT SYSTEM AND TIME-OF-FLIGHT SYSTEM
    6.
    发明申请
    METHOD FOR CALIBRATING A TIME-OF-FLIGHT SYSTEM AND TIME-OF-FLIGHT SYSTEM 审中-公开

    公开(公告)号：US20200271765A1

    公开(公告)日：2020-08-27

    申请号：US16648462

    申请日：2018-09-21

    Applicant: ams AG

    Inventor： Kerry Glover ,  Manfred Lueger ,  Robert Kappel ,  Christian Mautner ,  Mario Manninger

    IPC: G01S7/497 ,  G01S7/487

    Abstract: A method is presented for calibrating a time-of-flight system having a time-of-flight sensor located behind a cover plate. The method involves emitting a plurality of sending pulses of light in response to respective trigger pulses of a control signal and detecting received pulses of light. Respective difference values are determined which are representative of a time period between one of the sending pulses and one of the received pulses. The difference values are accumulated into a number of bins of at least one histogram. The method further involves recording at least one crosstalk response in the histogram within a predetermined range of bins, and calibrating the histogram using the recorded crosstalk response. Finally, an output signal is generated which is indicative of a time-of-flight based on an evaluation of the calibrated histogram.

    Time-to-digital converter and conversion method
    8.
    发明授权
    Time-to-digital converter and conversion method 审中-公开

    公开(公告)号：US10671025B2

    公开(公告)日：2020-06-02

    申请号：US16470410

    申请日：2017-12-08

    Applicant: ams AG

    Inventor： Christian Mautner ,  Friedrich Bahnmueller ,  Friedrich Laengauer ,  Robert Kappel

    IPC: H03M1/50 ,  G04F10/00 ,  H03K23/00 ,  H03L7/099 ,  H03M1/12 ,  H03L7/089 ,  H03L7/081 ,  H03M1/10

    Abstract: A time-to-digital converter arrangement has a ring oscillator with a plurality of inverting elements and a first and a second counter coupled to the ring oscillator. The first counter is configured to increment a first counter value if a positive edge transition is present at one of the inverting elements. The second counter is configured to increment a second counter value if a negative edge transition is present at the one of the inverting elements. A storage element stores the first and the second counter value and logical states of the plurality of inverting elements. A decoder coupled to the storage element selects one of the first and the second counter value as a valid value based on an evaluation of the stored logical states, and outputs a total counter value based on the valid value and the stored logical states.

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