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    Reducing peak current in memory systems
    1.
    发明授权
    Reducing peak current in memory systems 有权
    降低内存系统中的峰值电流

    公开(公告)号：US09043590B2

    公开(公告)日：2015-05-26

    申请号：US14055144

    申请日：2013-10-16

    Applicant: Apple Inc.

    Inventor： Ori Isachar ,  Julian Vlaiko ,  Gil Semo ,  Atai Levy

    IPC: G06F3/06 ,  G06F1/32

    CPC classification number: G06F3/0659 ,  G06F1/3225 ,  G06F3/0604 ,  G06F3/0683

    Abstract: A memory device includes a plurality of memory cells, a token input interface, a token output interface and control circuitry. The control circuitry is configured to accept a storage command, to condition execution of at least a part of the storage command on a presence of a token pulse on the token input interface, to execute the storage command, including the conditioned part, in the memory cells upon reception of the token pulse on the token input interface, and to reproduce the token pulse on the token output interface upon completion of the execution.

    Abstract translation: 存储器件包括多个存储器单元，令牌输入接口，令牌输出接口和控制电路。 控制电路被配置为接受存储命令，以在令牌输入接口上存在令牌脉冲的情况下调节存储命令的至少一部分的执行，以在存储器中执行包括调节部分的存储命令 在令牌输入接口上接收到令牌脉冲，并且在完成执行时在令牌输出接口上再现令牌脉冲。

    Redundancy schemes for non-volatile memory using parity zones having new and old parity blocks
    2.
    发明授权
    Redundancy schemes for non-volatile memory using parity zones having new and old parity blocks 有权
    使用具有新旧奇偶校验块的奇偶校验区的非易失性存储器的冗余方案

    公开(公告)号：US08914670B2

    公开(公告)日：2014-12-16

    申请号：US13670604

    申请日：2012-11-07

    Applicant: Apple Inc.

    Inventor： Etai Zaltsman ,  Julian Vlaiko ,  Ori Moshe Stern ,  Avraham Poza Meir

    IPC: G06F11/00

    CPC classification number: G06F11/108

    Abstract: A method includes, in a non-volatile memory that includes multiple memory blocks, defining a redundancy zone that includes at least an old parity block, a new parity block and multiple active blocks of which one block is defined as an open block. Data is stored in the redundancy zone and the stored data is protected, such that new input data is stored in the open block, redundancy information for the active blocks including the open block is stored in the new parity block, and the redundancy information for the active blocks excluding the open block is stored in the old parity block. Upon filling the open block and the new parity block, an alternative block is assigned to serve as the open block and the new parity block is assigned to serve as the old parity block.

    Abstract translation: 一种方法包括在包括多个存储器块的非易失性存储器中，定义包括至少一个旧奇偶校验块，新奇偶校验块和多个活动块的冗余区，其中一个块被定义为开放块。 将数据存储在冗余区域中，并且存储的数据被保护，使得新的输入数据被存储在开放块中，用于包括打开块的活动块的冗余信息被存储在新的奇偶校验块中，并且冗余信息用于 不包括打开块的活动块存储在旧的奇偶校验块中。 在填充开放块和新的奇偶校验块时，分配替代块用作开放块，并且新的奇偶校验块被分配用作旧的奇偶校验块。

    REDUCING PEAK CURRENT IN MEMORY SYSTEMS
    3.
    发明申请
    REDUCING PEAK CURRENT IN MEMORY SYSTEMS 审中-公开
    降低存储系统中的峰值电流

    公开(公告)号：US20140047200A1

    公开(公告)日：2014-02-13

    申请号：US14055144

    申请日：2013-10-16

    Applicant: Apple Inc.

    Inventor： Ori Isachar ,  Julian Vlaiko ,  Gil Semo ,  Atai Levy

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F1/3225 ,  G06F3/0604 ,  G06F3/0683

    Abstract: A memory device includes a plurality of memory cells, a token input interface, a token output interface and control circuitry. The control circuitry is configured to accept a storage command, to condition execution of at least a part of the storage command on a presence of a token pulse on the token input interface, to execute the storage command, including the conditioned part, in the memory cells upon reception of the token pulse on the token input interface, and to reproduce the token pulse on the token output interface upon completion of the execution.

    Abstract translation: 存储器件包括多个存储器单元，令牌输入接口，令牌输出接口和控制电路。 控制电路被配置为接受存储命令，以在令牌输入接口上存在令牌脉冲的情况下调节存储命令的至少一部分的执行，以在存储器中执行包括调节部分的存储命令 在令牌输入接口上接收到令牌脉冲，并且在完成执行时在令牌输出接口上再现令牌脉冲。

    Fast wake-up of differential receivers using common mode decoupling capacitors
    6.
    发明授权
    Fast wake-up of differential receivers using common mode decoupling capacitors 有权
    使用共模去耦电容快速唤醒差分接收器

    公开(公告)号：US09229502B2

    公开(公告)日：2016-01-05

    申请号：US13649759

    申请日：2012-10-11

    Applicant: Apple Inc.

    Inventor： Julian Vlaiko

    IPC: G06F1/26 ,  G06F1/32 ,  H04L12/12

    CPC classification number: G06F1/26 ,  G06F1/3203 ,  G06F1/3209 ,  H04L12/12

    Abstract: Embodiments of an AC coupled bus charging system are disclosed that may allow for different charging currents. The charging system may include a charging circuit and a control circuit. The charging circuit may be operable to controllably select different charging currents dependent upon the output of the control circuit.

    Abstract translation: 公开了可以允许不同充电电流的AC耦合总线充电系统的实施例。 充电系统可以包括充电电路和控制电路。 充电电路可操作以可控地选择取决于控制电路的输出的不同充电电流。

    Efficient storage of error correction information in DRAM
    8.
    发明授权
    Efficient storage of error correction information in DRAM 有权
    有效地存储DRAM中的纠错信息

    公开(公告)号：US08650465B2

    公开(公告)日：2014-02-11

    申请号：US13899903

    申请日：2013-05-22

    Applicant: Apple Inc.

    Inventor： Julian Vlaiko

    IPC: H03M13/00

    CPC classification number: G06F11/1044 ,  G06F11/1048 ,  H03M13/05 ,  H03M13/19 ,  H03M13/2707

    Abstract: A method for data storage includes encoding input data with an Error Correction Code (ECC), to produce encoded data. The encoded data is formatted in a super-frame consisting of a given number of burst sequences arranged in parallel, each burst sequence consisting of one or more bursts of multiple bytes of the encoded data. The burst sequences of the super-frame are stored in respective memory devices over a single data bus having a bus width, in bytes, that is equal to the given number.

    Abstract translation: 用于数据存储的方法包括用错误校正码（ECC）对输入数据进行编码，以产生编码数据。 编码数据被格式化为由并行布置的给定数目的突发序列组成的超帧，每个突发序列由编码数据的多个字节的一个或多个突发组成。 超帧的突发序列通过单个数据总线存储在相应的存储器件中，该数据总线具有等于给定数量的总线宽度（以字节为单位）。

    Hierarchical data storage system
    9.
    发明授权
    Hierarchical data storage system 有权
    分层数据存储系统

    公开(公告)号：US09405705B2

    公开(公告)日：2016-08-02

    申请号：US14548664

    申请日：2014-11-20

    Applicant: Apple Inc.

    Inventor： Michael Shachar ,  Barak Rotbard ,  Oren Golov ,  Uri Perlmutter ,  Dotan Sokolov ,  Julian Vlaiko ,  Yair Schwartz

    IPC: G06F12/00 ,  G06F12/12 ,  G06F12/06 ,  G06F13/16 ,  G06F12/02 ,  G06F3/06 ,  G06F13/18

    CPC classification number: G06F12/12 ,  G06F3/0628 ,  G06F3/0683 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/1657 ,  G06F13/1668 ,  G06F13/18 ,  G06F2212/1024 ,  G06F2212/7208

    Abstract: A data storage system includes a plurality of non-volatile memory devices arranged in one or more sets, a main controller and one or more processors. The main controller is configured to accept commands from a host and to convert the commands into recipes. Each recipe includes a list of multiple memory operations to be performed sequentially in the non-volatile memory devices belonging to one of the sets. Each of the processors is associated with a respective set of the non-volatile memory devices, and is configured to receive one or more of the recipes from the main controller and to execute the memory operations specified in the received recipes in the non-volatile memory devices belonging to the respective set.

    Abstract translation: 数据存储系统包括以一个或多个集合排列的多个非易失性存储器件，主控制器和一个或多个处理器。 主控制器配置为接受来自主机的命令，并将命令转换为配方。 每个配方包括要在属于其中一个组的非易失性存储器件中顺序执行的多个存储器操作的列表。 每个处理器与相应的一组非易失性存储器设备相关联，并且被配置为从主控制器接收一个或多个配方并且执行在非易失性存储器中接收的配方中指定的存储器操作 属于相应集合的设备。

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