公开(公告)号：US20140273292A1

公开(公告)日：2014-09-18

申请号：US14205673

申请日：2014-03-12

Applicant: Applied Materials, Inc.

Inventor： NICOLAS POSSEME ,  OLIVIER JOUBERT ,  THIBAUT DAVID ,  THORSTEN LILL

IPC: H01L21/66 ,  H01L21/02 ,  H01L21/3065

CPC classification number: H01L21/3065 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/7834

Abstract: Embodiments of methods of forming silicon nitride spacers are provided herein. In some embodiments, a method of forming silicon nitride spacers atop a substrate includes: depositing a silicon nitride layer atop an exposed silicon containing layer and an at least partially formed gate stack disposed atop a substrate; modifying a portion of the silicon nitride layer by exposing the silicon nitride layer to a hydrogen or helium containing plasma that is substantially free of fluorine; and removing the modified portion of the silicon nitride layer by performing a wet cleaning process to form the silicon nitride spacers, wherein the wet cleaning process removes the modified portion of the silicon nitride layer selectively to the silicon containing layer.

Abstract translation: 本文提供了形成氮化硅间隔物的方法的实施例。 在一些实施例中，在衬底顶部形成氮化硅间隔物的方法包括：在暴露的含硅层和设置在衬底顶部的至少部分形成的栅极堆叠之上沉积氮化硅层; 通过将氮化硅层暴露于基本上不含氟的含氢或含氦的等离子体来修饰氮化硅层的一部分; 以及通过进行湿式清洗处理来形成所述氮化硅间隔物来去除所述氮化硅层的修饰部分，其中所述湿式清洁工艺选择性地将所述氮化硅层的修饰部分去除所述含硅层。

公开(公告)号：US20140273297A1

公开(公告)日：2014-09-18

申请号：US14204668

申请日：2014-03-11

Applicant: APPLIED MATERIALS, INC.

Inventor： SAMER BANNA ,  OLIVIER JOUBERT ,  LEI LIAN ,  MAXIME DARNON ,  NICOLAS POSSEME ,  LAURENT VALLIER

IPC: H01L21/66

CPC classification number: H01L22/26 ,  G03F7/70625 ,  H01L21/0273 ,  H01L21/3086 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/67253 ,  H01L22/12 ,  H01L22/20

Abstract: In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process.

Abstract translation: 在一些实施例中，在半导体制造工艺中控制光致抗蚀剂修剪工艺的方法可以包括在衬底的第一表面之上形成光致抗蚀剂层，其中光致抗蚀剂层包括具有要蚀刻到第一表面中的第一图案的下层 以及具有未蚀刻到所述基板的第一表面中的第二图案的上层; 在平行于基板的第一表面的方向上修整光致抗蚀剂层; 在修整过程中使用光学测量工具测量第二图案的修剪率; 以及将所述第二图案的修整率与所述第一图案的修剪率相关联，以在所述修整处理期间控制所述第一图案的修整率。

公开(公告)号：US20190259562A1

公开(公告)日：2019-08-22

申请号：US16405377

申请日：2019-05-07

Applicant: APPLIED MATERIALS, INC.

Inventor： LEONID DORF ,  TRAVIS KOH ,  OLIVIER LUERE ,  OLIVIER JOUBERT ,  PHILIP A. KRAUS ,  RAJINDER DHINDSA ,  JAMES ROGERS

IPC: H01J37/08 ,  H01J37/248

Abstract: Systems and methods for creating arbitrarily-shaped ion energy distribution functions using shaped-pulse-bias. In an embodiment, a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and modulating the amplitude of the wafer voltage to produce a predetermined number of pulses to determine an ion energy distribution function. In another embodiment a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and applying a ramp voltage to the electrode that overcompensates for ion current on the wafer or applying a ramp voltage to the electrode that undercompensates for ion current on the wafer.

公开(公告)号：US20200266022A1

公开(公告)日：2020-08-20

申请号：US16867034

申请日：2020-05-05

Applicant: APPLIED MATERIALS, INC.

Inventor： LEONID DORF ,  TRAVIS KOH ,  OLIVIER LUERE ,  OLIVIER JOUBERT ,  PHILIP A. KRAUS ,  RAJINDER DHINDSA ,  JAMES ROGERS

IPC: H01J37/08 ,  H01J37/32 ,  H01J37/248

Abstract: Systems and methods for creating arbitrarily-shaped ion energy distribution functions using shaped-pulse—bias. In an embodiment, a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and modulating the amplitude of the wafer voltage to produce a predetermined number of pulses to determine an ion energy distribution function. In another embodiment a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and applying a ramp voltage to the electrode that overcompensates for ion current on the wafer or applying a ramp voltage to the electrode that undercompensates for ion current on the wafer.

公开(公告)号：US20210343496A1

公开(公告)日：2021-11-04

申请号：US17377639

申请日：2021-07-16

Applicant: APPLIED MATERIALS, INC.

Inventor： LEONID DORF ,  TRAVIS KOH ,  OLIVIER LUERE ,  OLIVIER JOUBERT ,  PHILIP A. KRAUS ,  RAJINDER DHINDSA ,  JAMES ROGERS

IPC: H01J37/08 ,  H01J37/248 ,  H01J37/32

Abstract: Systems and methods for creating arbitrarily-shaped ion energy distribution functions using shaped-pulse-bias. In an embodiment, a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and modulating the amplitude of the wafer voltage to produce a predetermined number of pulses to determine an ion energy distribution function. In another embodiment a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and applying a ramp voltage to the electrode that overcompensates for ion current on the wafer or applying a ramp voltage to the electrode that undercompensates for ion current on the wafer.