Abstract:
The present invention provides a process sequence and related hardware for filling a hole with copper. The sequence comprises first forming a reliable barrier layer in the hole to prevent diffusion of the copper into the dielectric layer through which the hole is formed. One sequence comprises forming a generally conformal barrier layer over a patterned dielectric, etching the bottom of the hole, depositing a second barrier, and then filling the hole with copper. An alternative sequence comprises depositing a first barrier layer over a blanket dielectric layer, forming a hole through both the barrier layer and the dielectric layer, depositing a generally conformal second barrier layer in the hole, removing the barrier layer from the bottom of the hole, and selectively filling the hole with copper.
Abstract:
The present invention provides a method and apparatus for forming reliable interconnects in which the overlap of the line over the plug or via is minimized or eliminated. In one aspect, a barrier plug comprised of a conductive material, such as tungsten, is deposited over the via to provide an etch stop during line etching and to prevent diffusion of the metal, such as copper, into the surrounding dielectric material if the line is misaligned over the via. Additionally, the barrier plug prevents an overall reduction in resistance of the interconnect and enables reactive ion etching to be employed to form the metal line. In another aspect, reactive ion etching techniques are employed to selectively etch the metal line and the barrier layer to provide a controlled etching process which exhibits selectivity for the metal line, then the barrier and then the via or plug.
Abstract:
The present invention provides a process sequence and related hardware for filling a hole with copper. The sequence comprises first forming a reliable barrier layer in the hole to prevent diffusion of the copper into the dielectric layer through which the hole is formed. One sequence comprises forming a generally conformal barrier layer over a patterned dielectric, etching the bottom of the hole, depositing a second barrier, and then filling the hole with copper. An alternative sequence comprises depositing a first barrier layer over a blanket dielectric layer, forming a hole through both the barrier layer and the dielectric layer, depositing a generally conformal second barrier layer in the hole, removing the barrier layer from the bottom of the hole, and selectively filling the hole with copper.
Abstract:
The present invention generally provides a precleaning process prior to metallization for submicron features on substrates. The method includes cleaning the submicron features with radicals from a plasma of a reactive gas such as oxygen, a mixture of CF4/O2, or a mixture of He/NF3, wherein the plasma is preferably generated by a remote plasma source and the radicals are delivered to a chamber in which the substrate is disposed. Native oxides remaining in the submicron features are preferably reduced in a second step by treatment with radicals from a plasma containing hydrogen. Following the first or both precleaning steps, the features can be filled with metal by available metallization techniques which typically include depositing a barrier/liner layer on exposed dielectric surfaces prior to deposition of aluminum, copper, or tungsten. The precleaning and metallization steps can be conducted on available integrated processing platforms.
Abstract:
A method of forming a titanium silicide nitride (TiSiN) layer is described. A titanium nitride (TiN) layer is deposited on a substrate, the process chamber is purged to remove reaction by-products therefrom and than the titanium nitride (TiN) layer is exposed to a silicon-containing gas to form the titanium suicide nitride (TiSiN) layer. Alternatively, the substrate may be exposed to the silicon-containing gas in a process chamber different from the one used for the titanium nitride (TiN) layer deposition.