公开(公告)号：US20240128090A1

公开(公告)日：2024-04-18

申请号：US18530759

申请日：2023-12-06

Applicant: ASM IP Holding B.V.

Inventor： Eiichiro Shiba ,  Yoshinori Ota ,  René Henricus Jozef Vervuurt ,  Nobuyoshi Kobayashi ,  Akiko Kobayashi

IPC: H01L21/311 ,  H01L21/02

CPC classification number: H01L21/31116 ,  H01L21/02164 ,  H01L21/0217

Abstract: A method for fabricating a layer structure having a target topology profile in a step which has a side face and a lateral face, includes processes of: (a) depositing a dielectric layer on a preselected area of the substrate under first deposition conditions, wherein the dielectric layer has a portion whose resistance to fluorine and/or chlorine radicals under first dry-etching conditions is tuned; and (b) exposing the dielectric layer obtained in process (a) to the fluorine and/or chlorine radicals under the first dry-etching conditions, thereby removing at least a part of the portion of the dielectric layer, thereby forming a layer structure having the target topology profile on the substrate.

公开(公告)号：US10720337B2

公开(公告)日：2020-07-21

申请号：US16040859

申请日：2018-07-20

Applicant: ASM IP Holding B.V.

Inventor： Rene Henricus Jozef Vervuurt ,  Nobuyoshi Kobayashi ,  Takayoshi Tsutsumi ,  Masaru Hori

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/67

Abstract: An etching process is provided that includes a pre-clean process to remove a surface oxide of a dielectric material. The removal of the oxide can be executed through a thermal reaction and/or plasma process before the etch process. In some embodiments, the removal of the oxide increases etch process control and reproducibility and can improve the selectivity versus oxides.

公开(公告)号：US20250006489A1

公开(公告)日：2025-01-02

申请号：US18754246

申请日：2024-06-26

Applicant: ASM IP Holding B.V.

Inventor： Ranjit Borude ,  Bablu Mukherjee ,  René Henricus Jozef Vervuurt ,  Viljami Pore ,  Takayoshi Tsutsumi ,  Nobuyoshi Kobayashi ,  Masaru Hori

IPC: H01L21/02 ,  C23C16/30 ,  C23C16/32 ,  C23C16/34 ,  C23C16/40 ,  C23C16/455 ,  C23C16/517 ,  H01J37/32

Abstract: The disclosure relates to methods of depositing a material comprising silicon in a gap. The method comprises providing a substrate, the substrate comprising the gap, wherein the gap comprises an inner surface and exposing the substrate to a first plasma having high ion energy to modify predetermined areas of the gap inner surface. The method further comprises exposing the substrate to a second plasma having low ion energy to passivate the modified areas of the gap surface to form passivated modified areas on the gap surface and contacting the substrate with a vapor-phase silicon precursor to chemisorb the silicon precursor on unmodified areas of the gap for depositing material comprising silicon on the unmodified areas. The current disclosure further relates to a method of controlling chemisorption of a vapor-phase silicon precursor on a substrate, and to a semiconductor processing assembly for performing the methods according to the current disclosure.

公开(公告)号：US11961741B2

公开(公告)日：2024-04-16

申请号：US17192865

申请日：2021-03-04

Applicant: ASM IP Holding B.V.

Inventor： Eiichiro Shiba ,  Yoshinori Ota ,  René Henricus Jozef Vervuurt ,  Nobuyoshi Kobayashi ,  Akiko Kobayashi

IPC: H01L21/311 ,  H01L21/02

CPC classification number: H01L21/31116 ,  H01L21/02164 ,  H01L21/0217

Abstract: A method for fabricating a layer structure having a target topology profile in a step which has a side face and a lateral face, includes processes of: (a) depositing a dielectric layer on a preselected area of the substrate under first deposition conditions, wherein the dielectric layer has a portion whose resistance to fluorine and/or chlorine radicals under first dry-etching conditions is tuned; and (b) exposing the dielectric layer obtained in process (a) to the fluorine and/or chlorine radicals under the first dry-etching conditions, thereby removing at least a part of the portion of the dielectric layer, thereby forming a layer structure having the target topology profile on the substrate.

公开(公告)号：US20220359215A1

公开(公告)日：2022-11-10

申请号：US17724337

申请日：2022-04-19

Applicant: ASM IP Holding B.V.

Inventor： René Henricus Jozef Vervuurt ,  Takayoshi Tsutsumi ,  Masaru Hori ,  Nobuyoshi Kobayashi ,  Yoshinori Oda ,  Charles Dezelah

IPC: H01L21/3065 ,  H01L21/02 ,  C23C16/455

Abstract: The current disclosure relates to processes for selectively etching material from one surface of a semiconductor substrate over another surface of the semiconductor substrate. The disclosure further relates to assemblies for etching material from a surface of a semiconductor substrate. In the processes, a substrate comprising a first surface and a second surface is provided into a reaction chamber, an etch-priming reactant is provided into the reaction chamber in vapor phase; reactive species generated from plasma are provided into the reaction chamber for selectively etching material from the first surface. The etch-priming reactant is deposited on the first surface and the etch-priming reactant comprises a halogenated hydrocarbon. The halogenated hydrocarbon may comprise a head group and a tail group, and one or both of them may be halogenated.

公开(公告)号：US20210287912A1

公开(公告)日：2021-09-16

申请号：US17192865

申请日：2021-03-04

Applicant: ASM IP Holding B.V.

Inventor： Eiichiro Shiba ,  Yoshinori Ota ,  René Henricus Jozef Vervuurt ,  Nobuyoshi Kobayashi ,  Akiko Kobayashi

IPC: H01L21/311 ,  H01L21/02

Abstract: A method for fabricating a layer structure having a target topology profile in a step which has a side face and a lateral face, includes processes of: (a) depositing a dielectric layer on a preselected area of the substrate under first deposition conditions, wherein the dielectric layer has a portion whose resistance to fluorine and/or chlorine radicals under first dry-etching conditions is tuned; and (b) exposing the dielectric layer obtained in process (a) to the fluorine and/or chlorine radicals under the first dry-etching conditions, thereby removing at least a part of the portion of the dielectric layer, thereby forming a layer structure having the target topology profile on the substrate.

公开(公告)号：US10720334B2

公开(公告)日：2020-07-21

申请号：US16041044

申请日：2018-07-20

Applicant: ASM IP Holding B.V.

Inventor： Rene Henricus Jozef Vervuurt ,  Nobuyoshi Kobayashi ,  Takayoshi Tsutsumi ,  Masaru Hori

IPC: H01L21/306 ,  H01L21/3065 ,  H01L21/3213 ,  C23C16/02 ,  B81C1/00 ,  C30B31/00 ,  C30B33/08 ,  C30B33/12 ,  H01L21/311 ,  H01L21/308 ,  H01L21/3105

Abstract: In some embodiments, a selective cyclic (optionally dry) etching of a first surface of a substrate relative to a second surface of the substrate in a reaction chamber by chemical atomic layer etching comprises forming a modification layer using a first plasma and etching the modification layer. The first surface comprises carbon and/or nitride and the second surface does not comprise carbon and/or nitride.

公开(公告)号：US20200027740A1

公开(公告)日：2020-01-23

申请号：US16041044

申请日：2018-07-20

Applicant: ASM IP Holding B.V.

Inventor： Rene Henricus Jozef Vervuurt ,  Nobuyoshi Kobayashi ,  Takayoshi Tsutsumi ,  Masaru Hori

IPC: H01L21/3065 ,  H01L21/3213

Abstract: In some embodiments, a selective cyclic (optionally dry) etching of a first surface of a substrate relative to a second surface of the substrate in a reaction chamber by chemical atomic layer etching comprises forming a modification layer using a first plasma and etching the modification layer. The first surface comprises carbon and/or nitride and the second surface does not comprise carbon and/or nitride.

公开(公告)号：US20180286663A1

公开(公告)日：2018-10-04

申请号：US15472750

申请日：2017-03-29

Applicant: ASM IP Holding B.V. ,  National University Corporation Nagoya University

Inventor： Akiko Kobayashi ,  Masaru Zaitsu ,  Nobuyoshi Kobayashi ,  Masaru Hori

IPC: H01L21/02

CPC classification number: H01L21/0234 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02318 ,  H01L21/0332 ,  H01L21/0337

Abstract: A method of reforming an insulating film deposited on a substrate having a recess pattern constituted by a bottom and sidewalls, includes: providing the film deposited on the substrate having the recess pattern in an evacuatable reaction chamber, wherein a property of a portion of the film deposited on the sidewalls is inferior to that of a portion of the film deposited on a top surface of the substrate; adjusting a pressure of an atmosphere of the reaction chamber to 10 Pa or less, which atmosphere is constituted by H2 and/or He without a precursor and without a reactant; and applying RF power to the atmosphere of the pressure-adjusted reaction chamber to generate a plasma to which the film is exposed, thereby reforming the portion of the film deposited on the sidewalls to improve the property of the sidewall portion of the film.

公开(公告)号：US20220375744A1

公开(公告)日：2022-11-24

申请号：US17747197

申请日：2022-05-18

Applicant: ASM IP Holding B.V.

Inventor： Akiko Kobayashi ,  René Henricus Jozef Vervuurt ,  Nobuyoshi Kobayashi ,  Takayoshi Tsutsumi ,  Masaru Hori

IPC: H01L21/02 ,  C23C16/458 ,  C23C16/455 ,  C23C16/40

Abstract: Methods and related systems for topographically depositing a material on a substrate are disclosed. The substrate comprises a proximal surface and a gap feature. The gap feature comprises a sidewall and a distal surface. Exemplary methods comprise, in the given order: a step of positioning the substrate on a substrate support in a reaction chamber; a step of subjecting the substrate to a plasma pre-treatment; and, a step of selectively depositing a material on at least one of the proximal surface and the distal surface with respect to the sidewall. The step of subjecting the substrate to a plasma pre-treatment comprises exposing the substrate to at least one of fluorine-containing molecules, ions, and radicals.