公开(公告)号：US20190205280A1

公开(公告)日：2019-07-04

申请号：US15856799

申请日：2017-12-28

申请人： Advanced Micro Devices, Inc.

发明人： Vydhyanathan Kalyanasundharam ,  Eric Christopher Morton ,  Chen-Ping Yang ,  Amit P. Apte ,  Elizabeth M. Cooper

IPC分类号： G06F13/42 ,  G06F13/364 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0811

CPC分类号： G06F13/4282 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0824 ,  G06F13/1663 ,  G06F13/364 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/621 ,  G06F2213/0026

摘要： Systems, apparatuses, and methods for implementing a cancel and replay mechanism for ordered requests are disclosed. A system includes at least an ordering master, a memory controller, a coherent slave coupled to the memory controller, and an interconnect fabric coupled to the ordering master and the coherent slave. The ordering master generates a write request which is forwarded to the coherent slave on the path to memory. The coherent slave sends invalidating probes to all processing nodes and then sends an indication that the write request is globally visible to the ordering master when all cached copies of the data targeted by the write request have been invalidated. In response to receiving the globally visible indication, the ordering master starts a timer. If the timer expires before all older requests have become globally visible, then the write request is cancelled and replayed to ensure forward progress in the fabric and avoid a potential deadlock scenario.

公开(公告)号：US20190138465A1

公开(公告)日：2019-05-09

申请号：US15807151

申请日：2017-11-08

申请人： Advanced Micro Devices, Inc.

发明人： Vydhyanathan Kalyanasundharam ,  Amit P. Apte ,  Chen-Ping Yang

IPC分类号： G06F13/16 ,  G06F13/42 ,  G06F13/30

CPC分类号： G06F13/1642 ,  G06F13/1689 ,  G06F13/30 ,  G06F13/4234

摘要： Systems, apparatuses, and methods for routing traffic between clients and system memory are disclosed. A computing system includes system memory and one or more clients, each capable of generating memory access requests. The computing system also includes a communication fabric for transferring traffic between the clients and the system memory. The fabric includes master units for interfacing with clients and grouping write requests with a same target together. The fabric also includes slave units for interfacing with memory controllers and for sending a single write response when each write request in a group has been serviced. When the master unit receives the single write response for the group, it sends a respective acknowledgment response for each of the multiple write requests in the group to clients that generated the multiple write requests.

公开(公告)号：US10684965B2

公开(公告)日：2020-06-16

申请号：US15807151

申请日：2017-11-08

申请人： Advanced Micro Devices, Inc.

发明人： Vydhyanathan Kalyanasundharam ,  Amit P. Apte ,  Chen-Ping Yang

IPC分类号： G06F13/16 ,  G06F13/30 ,  G06F13/42

摘要： Systems, apparatuses, and methods for routing traffic between clients and system memory are disclosed. A computing system includes system memory and one or more clients, each capable of generating memory access requests. The computing system also includes a communication fabric for transferring traffic between the clients and the system memory. The fabric includes master units for interfacing with clients and grouping write requests with a same target together. The fabric also includes slave units for interfacing with memory controllers and for sending a single write response when each write request in a group has been serviced. When the master unit receives the single write response for the group, it sends a respective acknowledgment response for each of the multiple write requests in the group to clients that generated the multiple write requests.

公开(公告)号：US10540316B2

公开(公告)日：2020-01-21

申请号：US15856799

申请日：2017-12-28

申请人： Advanced Micro Devices, Inc.

发明人： Vydhyanathan Kalyanasundharam ,  Eric Christopher Morton ,  Chen-Ping Yang ,  Amit P. Apte ,  Elizabeth M. Cooper

IPC分类号： G06F13/00 ,  G06F13/42 ,  G06F12/0806 ,  G06F12/0808 ,  G06F13/364 ,  G06F12/0811

摘要： Systems, apparatuses, and methods for implementing a cancel and replay mechanism for ordered requests are disclosed. A system includes at least an ordering master, a memory controller, a coherent slave coupled to the memory controller, and an interconnect fabric coupled to the ordering master and the coherent slave. The ordering master generates a write request which is forwarded to the coherent slave on the path to memory. The coherent slave sends invalidating probes to all processing nodes and then sends an indication that the write request is globally visible to the ordering master when all cached copies of the data targeted by the write request have been invalidated. In response to receiving the globally visible indication, the ordering master starts a timer. If the timer expires before all older requests have become globally visible, then the write request is cancelled and replayed to ensure forward progress in the fabric and avoid a potential deadlock scenario.

公开(公告)号：US12093689B2

公开(公告)日：2024-09-17

申请号：US17032301

申请日：2020-09-25

申请人： ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

发明人： Benjamin Tsien ,  Alexander J. Branover ,  John Petry ,  Chen-Ping Yang ,  Rostyslav Kyrychynskyi ,  Vydhyanathan Kalyanasundharam

IPC分类号： G06F11/14 ,  G06F1/30 ,  G06F9/30 ,  G06F9/38 ,  G06F9/4401 ,  G06F9/46 ,  G06F13/40

CPC分类号： G06F9/3005 ,  G06F9/3877 ,  G06F9/4418 ,  G06F9/463 ,  G06F13/4022

摘要： A processing system that includes a shared data fabric resets a first client processor while operating a second client processor. The first client processor is instructed to stop making requests to one or more devices of the shared data fabric. Status communications are blocked between the first client processor and a memory controller, the second client processor, or both, such that the first client processor enters a temporary offline state. The first client processor is indicated as being non-coherent. Accordingly, when the processor is reset some errors and efficiency losses due messages sent during or prior to the reset are prevented.