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42 条记录 (耗时 0.024 秒)

    Process to increase tin thickness
    5.
    发明授权
    Process to increase tin thickness 失效
    增加锡厚度的工艺

    公开(公告)号：US4676866A

    公开(公告)日：1987-06-30

    申请号：US837482

    申请日：1986-03-07

    申请人： Thomas E. Tang ,  Che-Chia Wei ,  Roger A. Haken ,  Thomas C. Holloway

    发明人： Thomas E. Tang ,  Che-Chia Wei ,  Roger A. Haken ,  Thomas C. Holloway

    IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/11 ,  C23F1/02 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

    CPC分类号： H01L27/11526 ,  H01L21/32053 ,  H01L21/76895 ,  H01L27/105 ,  H01L27/1108 ,  H01L27/11543

    摘要： A local interconnect system for VLSI integrated circuits. During self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a conductive titanium nitride layer is formed overall. A second titanium layer is then deposited overall and again reacted, to thicken the nitride layer without increasing the thickness of the silicide layers. This conductive layer is patterned and etched to provide local interconnects with a sheet resistance of the order to ten ohms per square, and also etch stops. Moreover, this local interconnect level permits contacts to be misaligned with the moat boundary, since the titanium nitride local interconnect layer can be overlapped from the moat up on to the field oxide to provide a bottom contact and diffusion barrier for a contact hole which is subsequently etched through the interlevel oxide. This local interconnect capability fulfills all of the functions which a buried contact capability fulfill, and fulfills other functions as well.

    摘要翻译： 用于VLSI集成电路的局部互连系统。 在氮气气氛中暴露的山沟和栅极区域的自对准硅化过程中，整体形成导电氮化钛层。 然后将第二钛层整体沉积并再次反应，以增加氮化物层而不增加硅化物层的厚度。 对该导电层进行图案化和蚀刻，以提供局部互连，其平面电阻为10欧姆/平方，并且也蚀刻停止。 此外，这种局部互连级别允许接触与护城河边界不对准，因为氮化钛局部互连层可以从护壕向上叠加到场氧化物上，以提供用于接触孔的底部接触和扩散屏障 通过层间氧化物蚀刻。 这种局部互连功能可以满足埋入式接触能力的所有功能，并满足其他功能。

    VLSI interconnect method and structure
    6.
    发明授权
    VLSI interconnect method and structure 失效
    VLSI互连方法和结构

    公开(公告)号：US5302539A

    公开(公告)日：1994-04-12

    申请号：US530492

    申请日：1990-05-29

    申请人： Roger A. Haken ,  Thomas C. Holloway

    发明人： Roger A. Haken ,  Thomas C. Holloway

    IPC分类号： H01L21/311 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L21/283 ,  H01L21/336

    CPC分类号： H01L27/11526 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3211 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/823835 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/11543 ,  Y10S257/915

    摘要： A local interconnect system for VLSI integrated circuits. During self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a conductive titanium nitride layer is formed overall. Normally this conductive layer is stripped to avoid shorting out devices. However, the present invention patterns this conductive layer, thereby providing a local interconnect with the sheet resistance of the order of one ohm per square. Moreover, this local interconnect level permits contacts to be misaligned with the moat boundary, since the titanium nitride local interconnect layer can be overlapped from the moat up on to the field oxide to provide a bottom contact and diffusion barrier for a contact hole which is subsequently etched through the interlevel oxide. This local interconnect level fulfills all of the functions which a buried contact layer could fulfill, and fulfills other functions as well.

    摘要翻译： 用于VLSI集成电路的局部互连系统。 在氮气气氛中暴露的山沟和栅极区域的自对准硅化过程中，整体形成导电氮化钛层。 通常，该导电层被剥离以避免短路器件。 然而，本发明对该导电层进行了图案化，从而提供了具有每平方一欧姆数量级的薄层电阻的局部互连。 此外，这种局部互连级别允许接触与护城河边界不对准，因为氮化钛局部互连层可以从护壕向上叠加到场氧化物上，以提供用于接触孔的底部接触和扩散屏障 通过层间氧化物蚀刻。 这种局部互连级别可以满足掩埋接触层可以实现的所有功能，并实现其他功能。

    Integrated circuit device and process with tin capacitors
    9.
    发明授权
    Integrated circuit device and process with tin capacitors 失效
    集成电路器件和工艺与锡电容器

    公开(公告)号：US4811078A

    公开(公告)日：1989-03-07

    申请号：US938654

    申请日：1986-12-05

    申请人： Howard L. Tigelaar ,  Roger A. Haken ,  Thomas C. Holloway

    发明人： Howard L. Tigelaar ,  Roger A. Haken ,  Thomas C. Holloway

    IPC分类号： H01L21/768 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/11 ,  H01L29/78 ,  H01L27/02 ,  H01L29/34

    CPC分类号： H01L27/11526 ,  H01L21/76895 ,  H01L27/105 ,  H01L27/1108 ,  H01L27/11543 ,  H01L27/11546 ,  Y10S257/915

    摘要： A new integrated circuit structure, wherein a TiN thin film layer 129 and another patterned thin film layer 124 preferably comprising polysilicon are separated (in some locations) by a thin dielectric 132 to define capacitors. At various other locations, the TiN layers 129 also makes contact to the polysilicon layer 124 (which will be silicide-clad at these locations), makes contact to n+ substrate regions 134 and p+ substrate regions 136, and also to provide a contact pad for a third patterned thin film conductor layer which overlies the other two. One important class of embodiments provides a floating-memory cell. wherein the floating gate 120 is made of polysilicon, but the control gate 142 consists predominantly of titanium nitride. A novel process for forming the titanium nitride control gate 142 and simultaneously forming titanium nitride local interconnect lines 149 is also disclosed.

    摘要翻译： 新的集成电路结构，其中优选地包括多晶硅的TiN薄膜层129和另一图案化薄膜层124通过薄的电介质132分离（在一些位置）以限定电容器。 在各种其他位置处，TiN层129还与多晶硅层124（在这些位置处将被硅化物包覆）接触，与n +衬底区域134和p +衬底区域136接触，并且还提供用于 第三图案化薄膜导体层，覆盖在另外两个。 一个重要的实施例类型提供了浮动存储单元。 其中浮置栅极120由多晶硅制成，但是控制栅极142主要由氮化钛组成。 还公开了用于形成氮化钛控制栅极142并同时形成氮化钛局部互连线149的新颖工艺。

    Device and process with doubled capacitors
    10.
    发明授权
    Device and process with doubled capacitors 失效
    具有双电容器的器件和工艺

    公开(公告)号：US4811076A

    公开(公告)日：1989-03-07

    申请号：US938653

    申请日：1986-12-05

    申请人： Howard L. Tigelaar ,  James L. Paterson ,  Roger A. Haken ,  Thomas C. Holloway

    发明人： Howard L. Tigelaar ,  James L. Paterson ,  Roger A. Haken ,  Thomas C. Holloway

    IPC分类号： H01L21/765 ,  H01L21/768 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/11 ,  H01L29/78 ,  H01L23/48 ,  H01L27/02

    CPC分类号： H01L27/11526 ,  H01L21/765 ,  H01L21/76895 ,  H01L27/105 ,  H01L27/1108 ,  H01L27/11543 ,  Y10S257/915

    摘要： An integrated circuit including doubled capacitors (metal/dielectric/TiN/dielectric/polysilicon). This structure is preferably made using a patterned interlevel oxide/nitride layer to split a polycide layer, i.e. at some locations the polycide layer has low sheet resistance and at other locations the polycide layer is vertically split to provide two layers (TiN and unsilicided polysilicon), which are separated by the interlevel oxide/nitride. A double contact etch is used before the first metal interconnect layer is deposited, so that the metal makes ohmic contact to underlying silicide or silicon or TiN in some locations, and in others provides insulated metal top plates over TiN/polysilicon capacitance to provide doubled capacitors.

    摘要翻译： 包括双电容器（金属/电介质/ TiN /电介质/多晶硅）的集成电路。 该结构优选使用图案化的层间氧化物/氮化物层来分裂多晶硅化合物层，即在一些位置处，多晶硅化物层具有低的薄层电阻，并且在其它位置处，多晶硅化物层被垂直分裂以提供两层（TiN和未硅化的多晶硅） ，其被层间氧化物/氮化物分离。 在沉积第一金属互连层之前使用双接触蚀刻，使得金属在一些位置中与下面的硅化物或硅或TiN发生欧姆接触，并且其它的在TiN /多晶硅电容上提供绝缘金属顶板以提供双重电容 。