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公开(公告)号：US20130168700A1
公开(公告)日：2013-07-04
申请号：US13806534
申请日：2010-06-24
申请人： Akihiko Furukawa , Yasuhiro Kagawa , Naruhisa Miura , Shiro Hino , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Masayuki Imaizumi
发明人： Akihiko Furukawa , Yasuhiro Kagawa , Naruhisa Miura , Shiro Hino , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Masayuki Imaizumi
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L21/0485 , H01L27/088 , H01L29/0696 , H01L29/45 , H01L29/6606 , H01L29/66068 , H01L29/7805 , H01L29/7815
摘要： In a high speed switching power semiconductor device having a sense pad, a high voltage is generated during switching operations in well regions under the sense pad due to a displacement current flowing through its flow path with a resistance, whereby the power semiconductor device sometimes breaks down by dielectric breakdown of a thin insulating film such as a gate insulating film. In a power semiconductor device according to the invention, sense-pad well contact holes are provided on well regions positioned under the sense pad and penetrate a field insulating film thicker than the gate insulating film to connect to the source pad, thereby improving reliability.
摘要翻译： 在具有感测焊盘的高速开关电力半导体器件中，由于位移电流通过其流动路径而具有电阻，在感测焊盘下的阱区域的开关操作期间产生高电压，由此功率半导体器件有时会分解 通过诸如栅极绝缘膜的薄绝缘膜的电介质击穿。 在根据本发明的功率半导体器件中，感测焊盘井接触孔设置在位于感测焊盘下方的阱区上，并穿透比栅极绝缘膜更厚的场绝缘膜以连接到源极焊盘，从而提高可靠性。
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公开(公告)号：US09293572B2
公开(公告)日：2016-03-22
申请号：US13806534
申请日：2010-06-24
申请人： Akihiko Furukawa , Yasuhiro Kagawa , Naruhisa Miura , Shiro Hino , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Masayuki Imaizumi
发明人： Akihiko Furukawa , Yasuhiro Kagawa , Naruhisa Miura , Shiro Hino , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Masayuki Imaizumi
CPC分类号： H01L29/78 , H01L21/0485 , H01L27/088 , H01L29/0696 , H01L29/45 , H01L29/6606 , H01L29/66068 , H01L29/7805 , H01L29/7815
摘要： In a high speed switching power semiconductor device having a sense pad, a high voltage is generated during switching operations in well regions under the sense pad due to a displacement current flowing through its flow path with a resistance, whereby the power semiconductor device sometimes breaks down by dielectric breakdown of a thin insulating film such as a gate insulating film. In a power semiconductor device according to the invention, sense-pad well contact holes are provided on well regions positioned under the sense pad and penetrate a field insulating film thicker than the gate insulating film to connect to the source pad, thereby improving reliability.
摘要翻译： 在具有感测焊盘的高速开关电力半导体器件中，由于位移电流通过其流动路径而具有电阻，在感测焊盘下的阱区域的开关操作期间产生高电压，由此功率半导体器件有时会分解 通过诸如栅极绝缘膜的薄绝缘膜的电介质击穿。 在根据本发明的功率半导体器件中，感测焊盘井接触孔设置在位于感测焊盘下方的阱区上，并穿透比栅极绝缘膜更厚的场绝缘膜以连接到源极焊盘，从而提高可靠性。
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公开(公告)号：US20130020587A1
公开(公告)日：2013-01-24
申请号：US13639738
申请日：2011-02-08
申请人： Shiro Hino , Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Akihiko Furukawa , Yukiyasu Nakao , Masayuki Imaizumi
发明人： Shiro Hino , Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Akihiko Furukawa , Yukiyasu Nakao , Masayuki Imaizumi
IPC分类号： H01L29/161 , H01L21/336
CPC分类号： H01L29/1095 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1608 , H01L29/402 , H01L29/42372 , H01L29/66068 , H01L29/7395 , H01L29/7805 , H01L29/7811 , H01L29/8611
摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type which is formed on a first main surface of the semiconductor substrate, a second well region of a second conductivity type which is formed to surround a cell region of the drift layer, and a source pad for electrically connecting the second well regions and a source region of the cell region through a first well contact hole provided to penetrate a gate insulating film on the second well region, a second well contact hole provided to penetrate a field insulating film on the second well region and a source contact hole.
摘要翻译： 半导体器件包括第一导电类型的半导体衬底，形成在半导体衬底的第一主表面上的第一导电类型的漂移层，形成为围绕电池的第二导电类型的第二阱区域 漂移层的区域和用于通过设置成穿过第二阱区域上的栅极绝缘膜设置的第一阱接触孔电连接第二阱区域和电池区域的源极区域的源极焊盘，提供第二阱接触孔 以穿透第二阱区域上的场绝缘膜和源极接触孔。
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公开(公告)号：US09006819B2
公开(公告)日：2015-04-14
申请号：US13639738
申请日：2011-02-08
申请人： Shiro Hino , Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Akihiko Furukawa , Yukiyasu Nakao , Masayuki Imaizumi
发明人： Shiro Hino , Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Akihiko Furukawa , Yukiyasu Nakao , Masayuki Imaizumi
IPC分类号： H01L29/66 , H01L29/10 , H01L29/78 , H01L29/861 , H01L29/06 , H01L29/16 , H01L29/40 , H01L29/423 , H01L29/739
CPC分类号： H01L29/1095 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1608 , H01L29/402 , H01L29/42372 , H01L29/66068 , H01L29/7395 , H01L29/7805 , H01L29/7811 , H01L29/8611
摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type which is formed on a first main surface of the semiconductor substrate, a second well region of a second conductivity type which is formed to surround a cell region of the drift layer, and a source pad for electrically connecting the second well regions and a source region of the cell region through a first well contact hole provided to penetrate a gate insulating film on the second well region, a second well contact hole provided to penetrate a field insulating film on the second well region and a source contact hole.
摘要翻译： 半导体器件包括第一导电类型的半导体衬底，形成在半导体衬底的第一主表面上的第一导电类型的漂移层，形成为围绕电池的第二导电类型的第二阱区域 漂移层的区域和用于通过设置成穿过第二阱区域上的栅极绝缘膜设置的第一阱接触孔电连接第二阱区域和电池区域的源极区域的源极焊盘，提供第二阱接触孔 以穿透第二阱区域上的场绝缘膜和源极接触孔。
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公开(公告)号：US08492836B2
公开(公告)日：2013-07-23
申请号：US13500659
申请日：2009-10-14
申请人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Shiro Hino , Akihiko Furukawa
发明人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Shiro Hino , Akihiko Furukawa
IPC分类号： H01L29/66
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/42368 , H01L29/42372 , H01L29/66068
摘要： In a semiconductor device according to the present invention, a p-type well region disposed in an outer peripheral portion of the power semiconductor device is divided into two parts, that is, an inside and an outside, and a field oxide film having a greater film thickness than the gate insulating film is provided on a well region at the outside to an inside of an inner periphery of the well region. Therefore, it is possible to prevent, in the gate insulating film, a dielectric breakdown due to the voltage generated by the flow of the displacement current in switching.
摘要翻译： 在根据本发明的半导体器件中，设置在功率半导体器件的外周部分中的p型阱区被分成两部分，即内部和外部，并且具有更大的场氧化物膜 膜厚比栅极绝缘膜设置在外部的阱区域到阱区的内周的内侧。 因此，可以防止在栅极绝缘膜中由于切换中的位移电流的流动而产生的电压引起的电介质击穿。
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公开(公告)号：US20120205669A1
公开(公告)日：2012-08-16
申请号：US13500659
申请日：2009-10-14
申请人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Shiro Hino , Akihiko Furukawa
发明人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Shiro Hino , Akihiko Furukawa
IPC分类号： H01L29/16 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/42368 , H01L29/42372 , H01L29/66068
摘要： In a semiconductor device according to the present invention, a p-type well region disposed in an outer peripheral portion of the power semiconductor device is divided into two parts, that is, an inside and an outside, and a field oxide film having a greater film thickness than the gate insulating film is provided on a well region at the outside to an inside of an inner periphery of the well region. Therefore, it is possible to prevent, in the gate insulating film, a dielectric breakdown due to the voltage generated by the flow of the displacement current in switching.
摘要翻译： 在根据本发明的半导体器件中，设置在功率半导体器件的外周部分中的p型阱区被分成两部分，即内部和外部，并且具有更大的场氧化物膜 膜厚比栅极绝缘膜设置在外部的阱区域到阱区的内周的内侧。 因此，可以防止在栅极绝缘膜中由于切换中的位移电流的流动而产生的电压引起的电介质击穿。
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公开(公告)号：US20150108564A1
公开(公告)日：2015-04-23
申请号：US14400025
申请日：2013-03-12
申请人： Naruhisa Miura , Shiro Hino , Akihiko Furukawa , Yuji Abe , Shuhei Nakata , Masayuki Imaizumi , Yasuhiro Kagawa
发明人： Naruhisa Miura , Shiro Hino , Akihiko Furukawa , Yuji Abe , Shuhei Nakata , Masayuki Imaizumi , Yasuhiro Kagawa
IPC分类号： H01L29/78 , H01L29/16 , H01L29/423 , H01L29/10 , H01L29/08
CPC分类号： H01L29/7802 , H01L21/046 , H01L29/0615 , H01L29/0619 , H01L29/086 , H01L29/1033 , H01L29/1095 , H01L29/1608 , H01L29/42356 , H01L29/66068 , H01L29/66893 , H01L29/7813 , H01L29/7827 , H01L29/7836 , H01L29/8083
摘要： A source region of a MOSFET includes: a source contact region connected to a source pad; a source extension region adjacent to a channel region in a well region; and a source resistance control region arranged between the source extension region and the source contact region. The source resistance control region is different in an impurity concentration from the source extension region and the source contact region. These three regions are connected in series between the source pad and the channel region in the well region.
摘要翻译： MOSFET的源极区域包括：源极接触区域，连接到源极焊盘; 源极延伸区域，其邻近阱区域中的沟道区域; 以及源极电阻控制区域，其布置在源极延伸区域和源极接触区域之间。 源极电阻控制区域与源极延伸区域和源极接触区域的杂质浓度不同。 这三个区域串联连接在源极区和阱区中的沟道区之间。
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公开(公告)号：US09525057B2
公开(公告)日：2016-12-20
申请号：US14400025
申请日：2013-03-12
申请人： Naruhisa Miura , Shiro Hino , Akihiko Furukawa , Yuji Abe , Shuhei Nakata , Masayuki Imaizumi , Yasuhiro Kagawa
发明人： Naruhisa Miura , Shiro Hino , Akihiko Furukawa , Yuji Abe , Shuhei Nakata , Masayuki Imaizumi , Yasuhiro Kagawa
IPC分类号： H01L29/08 , H01L29/78 , H01L21/04 , H01L29/10 , H01L29/423 , H01L29/06 , H01L29/66 , H01L29/808 , H01L29/16
CPC分类号： H01L29/7802 , H01L21/046 , H01L29/0615 , H01L29/0619 , H01L29/086 , H01L29/1033 , H01L29/1095 , H01L29/1608 , H01L29/42356 , H01L29/66068 , H01L29/66893 , H01L29/7813 , H01L29/7827 , H01L29/7836 , H01L29/8083
摘要： A source region of a MOSFET includes: a source contact region connected to a source pad; a source extension region adjacent to a channel region in a well region; and a source resistance control region arranged between the source extension region and the source contact region. The source resistance control region is different in an impurity concentration from the source extension region and the source contact region. These three regions are connected in series between the source pad and the channel region in the well region.
摘要翻译： MOSFET的源极区域包括：源极接触区域，连接到源极焊盘; 源极延伸区域，其邻近阱区域中的沟道区域; 以及源极电阻控制区域，其布置在源极延伸区域和源极接触区域之间。 源极电阻控制区域与源极延伸区域和源极接触区域的杂质浓度不同。 这三个区域串联连接在源极区和阱区中的沟道区之间。
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公开(公告)号：US20140077232A1
公开(公告)日：2014-03-20
申请号：US14116067
申请日：2012-03-07
申请人： Shiro Hino , Naruhisa Miura , Akihiko Furukawa , Yukiyasu Nakao , Tomokatsu Watanabe , Masayoshi Tarutani , Yuji Ebiike , Masayuki Imaizumi , Sunao Aya
发明人： Shiro Hino , Naruhisa Miura , Akihiko Furukawa , Yukiyasu Nakao , Tomokatsu Watanabe , Masayoshi Tarutani , Yuji Ebiike , Masayuki Imaizumi , Sunao Aya
CPC分类号： H01L29/1608 , H01L21/0485 , H01L29/0615 , H01L29/0638 , H01L29/41766 , H01L29/45 , H01L29/66068 , H01L29/7802 , H01L29/7811 , H01L29/7816 , H01L29/7845 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device capable of suppressing time variation of a threshold voltage and a method of manufacturing the same. A semiconductor device according to the present invention comprises a drift layer formed on a semiconductor substrate, first well regions formed in a surface layer of the drift layer, being apart from one another, a gate insulating film formed, extending on the drift layer and each of the first well regions, a gate electrode selectively formed on the gate insulating film, a source contact hole penetrating through the gate insulating film and reaching the inside of each of the first well regions, and a residual compressive stress layer formed on at least a side surface of the source contact hole, in which a compressive stress remains.
摘要翻译： 能够抑制阈值电压的时间变化的半导体器件及其制造方法。 根据本发明的半导体器件包括形成在半导体衬底上的漂移层，形成在漂移层的表面层中的第一阱区彼此分开，形成在栅极绝缘膜上的栅极绝缘膜，在漂移层上延伸，每个 选择性地形成在栅极绝缘膜上的栅极电极，穿过栅极绝缘膜并到达每个第一阱区域的内部的源极接触孔以及至少形成在第一阱区上的残留压应力层， 源接触孔的侧表面，其中保持压缩应力。
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公开(公告)号：US09093361B2
公开(公告)日：2015-07-28
申请号：US14116067
申请日：2012-03-07
申请人： Shiro Hino , Naruhisa Miura , Akihiko Furukawa , Yukiyasu Nakao , Tomokatsu Watanabe , Masayoshi Tarutani , Yuji Ebiike , Masayuki Imaizumi , Sunao Aya
发明人： Shiro Hino , Naruhisa Miura , Akihiko Furukawa , Yukiyasu Nakao , Tomokatsu Watanabe , Masayoshi Tarutani , Yuji Ebiike , Masayuki Imaizumi , Sunao Aya
IPC分类号： H01L29/76 , H01L29/16 , H01L29/45 , H01L29/66 , H01L29/78 , H01L21/04 , H01L29/417 , H01L29/06
CPC分类号： H01L29/1608 , H01L21/0485 , H01L29/0615 , H01L29/0638 , H01L29/41766 , H01L29/45 , H01L29/66068 , H01L29/7802 , H01L29/7811 , H01L29/7816 , H01L29/7845 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device capable of suppressing time variation of a threshold voltage and a method of manufacturing the same. A semiconductor device according to the present invention comprises a drift layer formed on a semiconductor substrate, first well regions formed in a surface layer of the drift layer, being apart from one another, a gate insulating film formed, extending on the drift layer and each of the first well regions, a gate electrode selectively formed on the gate insulating film, a source contact hole penetrating through the gate insulating film and reaching the inside of each of the first well regions, and a residual compressive stress layer formed on at least a side surface of the source contact hole, in which a compressive stress remains.
摘要翻译： 能够抑制阈值电压的时间变化的半导体器件及其制造方法。 根据本发明的半导体器件包括形成在半导体衬底上的漂移层，形成在漂移层的表面层中的第一阱区彼此分开，形成在栅极绝缘膜上的栅极绝缘膜，在漂移层上延伸，每个 选择性地形成在栅极绝缘膜上的栅极电极，穿过栅极绝缘膜并到达每个第一阱区域的内部的源极接触孔以及至少形成在第一阱区上的残留压应力层， 源接触孔的侧表面，其中保持压缩应力。
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