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    Extended register addressing using prefix instruction
    3.
    发明授权
    Extended register addressing using prefix instruction 有权
    使用前缀指令进行扩展寄存器寻址

    公开(公告)号：US08601239B2

    公开(公告)日：2013-12-03

    申请号：US12827238

    申请日：2010-06-30

    申请人： Toshio Yoshida ,  Yasunobu Akizuki ,  Ryuichi Sunayama

    发明人： Toshio Yoshida ,  Yasunobu Akizuki ,  Ryuichi Sunayama

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30145 ,  G06F9/30101 ,  G06F9/30185

    摘要： A processor includes a storage unit storing an instruction, an instruction extension information register that includes a first area and a second area, an instruction decoding unit that decodes a first prefix instruction including first extension information extending an immediately following instruction written to the first area when the first prefix instruction is executed, and that decodes a second prefix instruction including the first extension information and a second extension information extending an instruction immediately following two instructions of the second prefix instruction, an instruction packing unit that generates a packed instruction including at least one of the first prefix instruction or the second prefix instruction, and the instruction immediately following the first prefix instruction or the second prefix instruction when the instruction decoding unit decodes the first prefix instruction or the second prefix instruction, an instruction execution unit that executes the packed instruction generated by the instruction packing unit.

    摘要翻译： 处理器包括存储指令的存储单元，包括第一区域和第二区域的指令扩展信息寄存器，指令解码单元，其对包含第一扩展信息的第一前缀指令进行解码，所述第一前缀指令包括第一扩展信息， 执行第一前缀指令，并且解码包括第一扩展信息的第二前缀指令和扩展紧跟在第二前缀指令的两个指令之后的指令的第二扩展信息;指令打包单元，其生成包括至少一个 第一前缀指令或第二前缀指令的指令，以及当指令解码单元解码第一前缀指令或第二前缀指令时紧跟在第一前缀指令或第二前缀指令之后的指令，执行指令执行单元， 剪切由指令包装单元生成的打包指令。

    Multithread processor and method of controlling multithread processor
    4.
    发明授权
    Multithread processor and method of controlling multithread processor 失效
    多线程处理器和控制多线程处理器的方法

    公开(公告)号：US08447959B2

    公开(公告)日：2013-05-21

    申请号：US12805630

    申请日：2010-08-10

    申请人： Toshio Yoshida

    发明人： Toshio Yoshida

    IPC分类号： G06F9/48

    CPC分类号： G06F9/3851 ,  G06F9/30127

    摘要： A plurality of register windows in a multithread processor are each provided for a corresponding thread and capable of storing data to be used for instruction processing in an arithmetic unit. A work register in the multithread processor is capable of mutually transferring data with respect to the register windows and the arithmetic unit. A multithread control unit in the multithread processor controls data transfer among the register windows, the work register and the arithmetic unit on the basis of an execution thread identifier identifying the thread to be executed in the arithmetic unit. This enables conducting the multithread processing at a high speed.

    摘要翻译： 多线程处理器中的多个寄存器窗口分别被提供给相应的线程并且能够存储用于在算术单元中进行指令处理的数据。 多线程处理器中的工作寄存器能够相对于寄存器窗口和算术单元相互传送数据。 多线程处理器中的多线程控制单元基于识别要在运算单元中执行的线程的执行线程标识符来控制寄存器窗口，工作寄存器和运算单元之间的数据传送。 这使得能够高速进行多线程处理。

    Processor decoding extension instruction to store plural address extension information in extension register for plural subsequent instructions
    5.
    发明授权
    Processor decoding extension instruction to store plural address extension information in extension register for plural subsequent instructions 有权
    处理器解码扩展指令，用于在多个后续指令的扩展寄存器中存储多个地址扩展信息

    公开(公告)号：US08281112B2

    公开(公告)日：2012-10-02

    申请号：US12338245

    申请日：2008-12-18

    申请人： Toshio Yoshida ,  Mikio Hondou

    发明人： Toshio Yoshida ,  Mikio Hondou

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30181 ,  G06F9/30101

    摘要： A processing unit has an extended register to which instruction extension information indicating an extension of an instruction can be set. An operation unit that, when instruction extension information is set to the extended register, executes a subsequent instruction following a first instruction for writing the instruction extension information into the extended register, extends the subsequent instruction based on the instruction extension information.

    摘要翻译： 处理单元具有扩展寄存器，可以设置指示扩展指令的指令扩展信息。 一种操作单元，当指令扩展信息被设置为扩展寄存器时，执行将指令扩展信息写入扩展寄存器的第一指令之后的后续指令，根据指令扩展信息来扩展后续指令。

    Processing unit
    7.
    发明授权
    Processing unit 有权
    处理单元

    公开(公告)号：US08001362B2

    公开(公告)日：2011-08-16

    申请号：US12633108

    申请日：2009-12-08

    申请人： Atsushi Fusejima ,  Takashi Suzuki ,  Toshio Yoshida ,  Yasunobu Akizuki

    发明人： Atsushi Fusejima ,  Takashi Suzuki ,  Toshio Yoshida ,  Yasunobu Akizuki

    IPC分类号： G06F9/38 ,  G06F9/46

    CPC分类号： G06F9/3851 ,  G06F9/3013 ,  G06F9/3857 ,  G06F11/3466 ,  G06F2201/88

    摘要： A processing unit includes a plurality of thread execution units each provided with a performance analysis circuit for measuring various types of events resulting from execution of instructions and a commit stack entry unit for controlling the completion of executed instructions and each executing a thread having a plurality of instructions, a commit scope register for storing instructions of completion candidates stored in each commit stack entry unit by execution by each thread execution unit and performing processing for completion of instructions included in the thread, and a thread selecting means for sending commit events of the instructions to a performance analysis circuit provided in each thread execution unit corresponding to the instructions when performing commit processing for instructions stored in the commit scope register.

    摘要翻译： 处理单元包括多个线程执行单元，每个线程执行单元具有用于测量执行指令的各种类型的事件的性能分析电路和用于控制执行指令完成的提交堆栈输入单元，并且每个线程执行单元执行具有多个 指令，用于通过每个线程执行单元的执行来存储存储在每个提交栈输入单元中的完成候选的指令的提交范围寄存器，并且执行用于完成包括在该线程中的指令的处理;线程选择装置，用于发送指令的提交事件 涉及在对存储在提交范围寄存器中的指令执行提交处理时对应于指令的每个线程执行单元中提供的性能分析电路。

    Instruction processing apparatus
    8.
    发明申请
    Instruction processing apparatus 审中-公开
    指令处理装置

    公开(公告)号：US20100106945A1

    公开(公告)日：2010-04-29

    申请号：US12654311

    申请日：2009-12-16

    申请人： Toshio Yoshida

    发明人： Toshio Yoshida

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/312

    CPC分类号： G06F9/3851 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3802 ,  G06F9/382 ,  G06F9/3838

    摘要： The present invention includes a decode section for simultaneously holding a plurality of instructions in one thread at a time and for decoding the held instructions; an execution pipeline capable of simultaneously executing each processing represented by the respective instructions belonging to different threads and decoded by the decode section; a reservation station for receiving the instructions decoded by the decode section and holding the instructions, if the decoded instructions are of sync attribute, until executable conditions are ready and thereafter dispatching the decoded instructions to the execution pipeline; a pre-decode section for confirming by a simple decoding, prior to decoding by the decode section, whether or not the instructions are of sync attribute; and an instruction buffer for suspending issuance to the decode section and holding the instructions subsequent to an instruction of sync attribute.

    摘要翻译： 本发明包括一个解码部分，用于一次同时在一个线程中保持多个指令并解码所保持的指令; 能够同时执行由属于不同线程并由解码部解码的各个指令所表示的每个处理的执行流水线; 如果所述解码指令是同步属性，则在所述可执行条件就绪之前，接收由所述解码部解码的指令并保持所述指令的保留站，并且此后将解码的指令分派到所述执行管线; 预解码部分，用于在由解码部分解码之前通过简单解码来确认指令是否是同步属性; 以及指令缓冲器，用于暂停向解码部分发布并保持在sync属性指令之后的指令。

    ARITHMETIC DEVICE
    9.
    发明申请
    ARITHMETIC DEVICE 失效
    算术设备

    公开(公告)号：US20100095306A1

    公开(公告)日：2010-04-15

    申请号：US12638760

    申请日：2009-12-15

    申请人： Norihito GOMYO ,  Toshio Yoshida ,  Ryuichi Sunayama

    发明人： Norihito GOMYO ,  Toshio Yoshida ,  Ryuichi Sunayama

    IPC分类号： G06F9/46 ,  G06F9/44 ,  G06F11/00 ,  G06F9/302

    CPC分类号： G06F9/3851 ,  G06F9/30083 ,  G06F9/3009 ,  G06F9/30189 ,  G06F9/3885

    摘要： An arithmetic device simultaneously processes a plurality of threads and may continue the process by minimizing the degradation of the entire performance although a hardware error occurs. An arithmetic device 100 includes: an instruction execution circuit 101 capable of selectively executing a mode in which the instruction sequences of a plurality of threads are executed and a mode in which the instruction sequence of a single thread is executed; and a switch indication circuit 102 instructing the instruction execution circuit 101 to switch a thread mode.

    摘要翻译： 算术装置同时处理多个线程，并且可以通过尽可能降低整个性能的劣化来继续该过程，尽管发生硬件错误。 算术装置100包括：指令执行电路101，其能够选择性地执行执行多个线程的指令序列的模式以及执行单线程的指令序列的模式; 和指示执行电路101切换线程模式的开关指示电路102。

    Instruction processing apparatus
    10.
    发明申请
    Instruction processing apparatus 有权
    指令处理装置

    公开(公告)号：US20100095095A1

    公开(公告)日：2010-04-15

    申请号：US12654159

    申请日：2009-12-11

    申请人： Toshio Yoshida

    发明人： Toshio Yoshida

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3851 ,  G06F9/30043 ,  G06F9/30127 ,  G06F9/3857

    摘要： An instruction processing apparatus includes a thread execution processing section executing threads each including plural instructions, a register file including a register window having plural registers, a current window pointer indicating a position of the register where the register window is possible to be inputted and outputted, a current register reading data held by the register window designated by the current window pointer to hold the data and a replacement buffer holding data transferred from the register file to the current register, a first transfer path transferring data in a register file to one of the replacement buffer, a second data transfer transferring data in a replacement buffer to one of the current registers, a calculation section executing a switching instruction of the register window, and a control section controlling, if the calculation section executes the switching instruction, the first data transfer path and the second data transfer path.

    摘要翻译： 一种指令处理装置，包括执行包括多个指令的线程的线程执行处理部分，包括具有多个寄存器的寄存器窗口的寄存器文件，指示可以输入和输出寄存器窗口的寄存器的位置的当前窗口指针， 当前寄存器读取由当前窗口指针指定的寄存器窗口保存的数据，以保存数据;以及替换缓冲器，保存从寄存器文件传送到当前寄存器的数据;第一传送路径，将寄存器文件中的数据传送到 替换缓冲器，将替换缓冲器中的数据传送到当前寄存器之一的第二数据传输;执行寄存器窗口的切换指令的计算部分;以及控制部分，如果所述计算部分执行所述切换指令，则控制所述第一数据 传输路径和第二数据传输路径。