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    Plug-in unit, a housing and an electronic apparatus
    2.
    发明授权
    Plug-in unit, a housing and an electronic apparatus 有权
    插件单元，外壳和电子设备

    公开(公告)号：US06991471B2

    公开(公告)日：2006-01-31

    申请号：US10788915

    申请日：2004-02-27

    申请人： Mitsuaki Hayashi ,  Akira Sawada ,  Kouichi Kuramitsu ,  Wataru Takano ,  Minoru Fujii ,  Hironori Tanaka

    发明人： Mitsuaki Hayashi ,  Akira Sawada ,  Kouichi Kuramitsu ,  Wataru Takano ,  Minoru Fujii ,  Hironori Tanaka

    IPC分类号： H01R12/00 ,  H05K1/00

    CPC分类号： G02B6/4452 ,  G02B6/3897 ,  G02B6/4292

    摘要： An electronic apparatus has a plug-in unit and a housing that can increase a number of optical modules connected thereto. In the plug-in unit, a first connector is connectable to an optical module connected to an optical cable. A connector housing accommodates the first connector and has an insertion part into which the optical module is inserted. An attachment lever is used for fixing the plug-in unit to the housing in which the plug-in unit is accommodated. The first connector is located on a back side of the plug-in unit opposite to a front side where the attachment lever is located.

    摘要翻译： 电子设备具有插入单元和壳体，其可以增加与其连接的多个光学模块。 在插件单元中，第一连接器可连接到连接到光缆的光学模块。 连接器壳体容纳第一连接器并且具有插入部件，光学模块插入该插入部分。 使用连接杆将插入单元固定到容纳插入单元的壳体上。 第一连接器位于插入单元的背面，与安装杆所在的前侧相对。

    Plug-in unit, a housing and an electronic apparatus
    3.
    发明申请
    Plug-in unit, a housing and an electronic apparatus 有权
    插件单元，外壳和电子设备

    公开(公告)号：US20050074222A1

    公开(公告)日：2005-04-07

    申请号：US10788915

    申请日：2004-02-27

    申请人： Mitsuaki Hayashi ,  Akira Sawada ,  Kouichi Kuramitsu ,  Wataru Takano ,  Minoru Fujii ,  Hironori Tanaka

    发明人： Mitsuaki Hayashi ,  Akira Sawada ,  Kouichi Kuramitsu ,  Wataru Takano ,  Minoru Fujii ,  Hironori Tanaka

    IPC分类号： G02B6/00 ,  G02B6/38 ,  G02B6/42 ,  H05K7/14

    CPC分类号： G02B6/4452 ,  G02B6/3897 ,  G02B6/4292

    摘要： An electronic apparatus has a plug-in unit and a housing that can increase a number of optical modules connected thereto. In the plug-in unit, a first connector is connectable to an optical module connected to an optical cable. A connector housing accommodates the first connector and has an insertion part into which the optical module is inserted. An attachment lever is used for fixing the plug-in unit to the housing in which the plug-in unit is accommodated. The first connector is located on a back side of the plug-in unit opposite to a front side where the attachment lever is located.

    摘要翻译： 电子设备具有插入单元和壳体，其可以增加与其连接的多个光学模块。 在插件单元中，第一连接器可连接到连接到光缆的光学模块。 连接器壳体容纳第一连接器并且具有插入部件，光学模块插入该插入部分。 使用连接杆将插入单元固定到容纳插入单元的壳体上。 第一连接器位于插入单元的背面，与安装杆所在的前侧相对。

    Semiconductor memory device
    7.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07251184B2

    公开(公告)日：2007-07-31

    申请号：US11400404

    申请日：2006-04-10

    申请人： Shuji Nakaya ,  Wataru Abe ,  Mitsuaki Hayashi

    发明人： Shuji Nakaya ,  Wataru Abe ,  Mitsuaki Hayashi

    IPC分类号： G11C8/00

    CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C17/12

    摘要： A semiconductor memory device is provided which has a hierarchical bit line structure and can perform a high-speed read operation even with a low voltage. A subarray 12 includes a first MOS transistor PD1 for charging a main bit line MBL1 and a second MOS transistor PS1 for charging a sub-bit line SBL1—1. The source electrode of the second MOS transistor PS1 is connected to a power source voltage, and the source electrode of the first MOS transistor PD1 is connected via a fourth MOS transistor PD2 to the power source voltage. Since there is not a resistance between the main bit line MBL1 and the sub-bit line SBL1—1, which is present if a transistor is used to achieve conduction therebetween, discharging of the main bit line and charging of the sub-bit line can be performed with high speed.

    摘要翻译： 提供一种具有分层位线结构并且即使在低电压下也能执行高速读取操作的半导体存储器件。 子阵列12包括用于对主位线MBL 1充电的第一MOS晶体管PD1和用于对子位线SBL 1 - 1充电的第二MOS晶体管PS 1。 第二MOS晶体管PS 1的源电极连接到电源电压，第一MOS晶体管PD1的源电极通过第四MOS晶体管PD2连接到电源电压。 由于在主位线MBL 1和子位线SBL 1 - 1之间没有电阻，如果使用晶体管来实现导通，则存在该位线之间的电阻，主位线 并且可以高速执行子位线的充电。

    Semiconductor memory device
    8.
    发明申请
    Semiconductor memory device 审中-公开
    半导体存储器件

    公开(公告)号：US20060120201A1

    公开(公告)日：2006-06-08

    申请号：US11267195

    申请日：2005-11-07

    申请人： Masakazu Kurata ,  Mitsuaki Hayashi

    发明人： Masakazu Kurata ,  Mitsuaki Hayashi

    IPC分类号： G11C8/00

    CPC分类号： G11C17/12

    摘要： According to a conventional semiconductor memory device, in a replica circuit composed of a plurality of dummy bit lines, an off leakage current of a transistor has been significantly increased with the advance of a semiconductor microfabrication technology, so that the dummy bit line has not been able to be charged to a desired potential due to the off leakage current when charging. As a result of this, since a charging period or a discharging period of the dummy bit line is also different from a desired period, the optimal operation timing may not be set. In a dummy memory cell array, in order to connect a drain region 21 and a first dummy bit line 25, the first dummy bit line 25 is connected via contact and via holes 28 through 30 and metal electrodes 23 and 24, while a second dummy bit line 46 does not contact to a drain region 47.

    摘要翻译： 根据传统的半导体存储器件，在由多个虚拟位线构成的复制电路中，随着半导体微细加工技术的发展，晶体管的截止漏电流已经显着增加，使得虚位线未被 能够在充电时由于断开的漏电流而被充电到期望的电位。 结果，由于虚拟位线的充电期间或放电期间也与期望的周期不同，所以可以不设定最佳​​的动作时机。 在虚拟存储单元阵列中，为了连接漏区21和第一虚位线25，第一虚位线25经由接触和通孔28至30和金属电极23和24连接，而第二虚位 位线46不与漏极区域47接触。

    Semiconductor device
    9.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20060002212A1

    公开(公告)日：2006-01-05

    申请号：US11025138

    申请日：2004-12-30

    申请人： Shuji Nakaya ,  Mitsuaki Hayashi ,  Masakazu Kurata

    发明人： Shuji Nakaya ,  Mitsuaki Hayashi ,  Masakazu Kurata

    IPC分类号： G11C7/00

    CPC分类号： G11C17/12 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C17/14 ,  G11C29/1201 ,  G11C29/14 ,  G11C2029/1202 ,  G11C2029/1204

    摘要： An output end and an inverted output end of a latch circuit that is connected to an output buffer circuit are switched with each other, and thereby, the relationship between the data of “0” or “1” and the drain of a memory cell is connected or not connected to a bit line is changed. In addition, an input of a sense amplifier is fixed at the grounding potential by means of a test control signal, and thereby, positive logic is confirmed in the case where the output of the output buffer circuit is “L,” and negative logic is confirmed in the case where the output of the output buffer circuit is “H.”

    摘要翻译： 连接到输出缓冲电路的锁存电路的输出端和反相输出端彼此切换，由此“0”或“1”的数据与存储单元的漏极之间的关系为 连接或未连接到位线被更改。 此外，读出放大器的输入通过测试控制信号固定在接地电位，从而在输出缓冲电路的输出为“L”的情况下确认正逻辑，而负逻辑为 在输出缓冲电路的输出为“H”的情况下确认。