公开(公告)号：US20120025294A1

公开(公告)日：2012-02-02

申请号：US13208454

申请日：2011-08-12

申请人： Masao SHINGU ,  Akira Takashima ,  Koichi Muraoka

发明人： Masao SHINGU ,  Akira Takashima ,  Koichi Muraoka

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/788 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/66825

摘要： There is provided a semiconductor device in which degradation of reliability originating in the interface between an upper insulating layer and an element isolation insulating layer is suppressed. The semiconductor device includes: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures. The element isolation insulating layer includes at least one of SiO2, SiN, and SiON, the upper insulating layer is an oxide containing at least one metal M selected from the group consisting of a rare earth metal, Y, Zr, and Hf, and Si, and respective lengths Lcharge, Ltop, and Lgate of the charge storage layer, the upper insulating layer, and the control electrode in a channel length direction satisfy the relation “Lcharge

摘要翻译： 提供一种半导体器件，其中抑制源于上绝缘层和元件隔离绝缘层之间的界面的可靠性的劣化。 半导体器件包括：半导体区域; 多个堆叠结构，其各自设置在所述半导体区域上，并且具有依次堆叠的隧道绝缘膜，电荷存储层，上绝缘层和控制电极; 设置在所述多个堆叠结构的侧面上的元件隔离绝缘层; 以及设置在半导体区域和多个堆叠结构中的源极 - 漏极区域。 元件隔离绝缘层包括SiO 2，SiN和SiON中的至少一种，上绝缘层是含有选自稀土金属，Y，Zr和Hf中的至少一种金属M的氧化物，Si ，并且沟道长度方向上的电荷存储层，上绝缘层和控制电极的各自的长度Lcharge，Ltop和Lgate满足关系“Lcharge

公开(公告)号：US09379320B2

公开(公告)日：2016-06-28

申请号：US13362832

申请日：2012-01-31

申请人： Masao Shingu ,  Akira Takashima ,  Koichi Muraoka

发明人： Masao Shingu ,  Akira Takashima ,  Koichi Muraoka

IPC分类号： H01L45/00 ,  H01L27/06 ,  H01L27/24 ,  H01L27/10

CPC分类号： H01L45/1273 ,  H01L27/101 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1675

摘要： According to one embodiment, a nonvolatile memory device includes a memory section. The memory section includes a first insulating layer, a second insulating layer and a pair of electrodes. The second insulating layer is formed on and in contact with the first insulating layer. The second insulating layer has at least one of a composition different from a composition of the first insulating layer and a phase state different from a phase state of the first insulating layer. The pair of electrodes is capable of passing a current through a current path along a boundary portion between the first insulating layer and the second insulating layer. An electrical resistance of the current path is changed by a voltage applied between the pair of electrodes.

摘要翻译： 根据一个实施例，非易失性存储器件包括存储器部分。 存储部分包括第一绝缘层，第二绝缘层和一对电极。 第二绝缘层形成在第一绝缘层上并与第一绝缘层接触。 第二绝缘层具有与第一绝缘层的组成不同的组成和与第一绝缘层的相位状态不同的相位状态中的至少一个。 一对电极能够使电流通过沿着第一绝缘层和第二绝缘层之间的边界部分的电流路径。 通过施加在该对电极之间的电压来改变电流路径的电阻。

公开(公告)号：US20100078704A1

公开(公告)日：2010-04-01

申请号：US12404648

申请日：2009-03-16

申请人： Tsunehiro Ino ,  Shosuke Fujii ,  Jun Fujiki ,  Akira Takashima ,  Masao Shingu ,  Daisuke Matsushita ,  Naoki Yasuda ,  Koichi Muraoka

发明人： Tsunehiro Ino ,  Shosuke Fujii ,  Jun Fujiki ,  Akira Takashima ,  Masao Shingu ,  Daisuke Matsushita ,  Naoki Yasuda ,  Koichi Muraoka

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/792 ,  H01L29/517 ,  H01L29/66833

摘要： A semiconductor storage element includes: a source region and a drain region provided in a semiconductor substrate; a tunnel insulating film provided on the semiconductor substrate between the source region and the drain region; a charge storage film provided on the tunnel insulating film; a block insulating film provided on the charge storage film; a gate electrode provided on the block insulating film; and a region containing a gas molecule, the region provided in a neighborhood of an interface between the charge storage film and the block insulating film.

摘要翻译： 半导体存储元件包括：设置在半导体衬底中的源极区域和漏极区域; 设置在所述源极区域和所述漏极区域之间的所述半导体衬底上的隧道绝缘膜; 设置在所述隧道绝缘膜上的电荷存储膜; 设置在电荷存储膜上的块状绝缘膜; 设置在所述块绝缘膜上的栅电极; 以及包含气体分子的区域，所述区域设置在电荷存储膜和块绝缘膜之间的界面附近。

公开(公告)号：US20080121979A1

公开(公告)日：2008-05-29

申请号：US11846251

申请日：2007-08-28

申请人： Yukie NISHIKAWA ,  Akira Takashima ,  Koichi Muraoka

发明人： Yukie NISHIKAWA ,  Akira Takashima ,  Koichi Muraoka

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42336 ,  H01L29/513

摘要： A nonvolatile semiconductor memory device includes: a tunneling insulating film; a floating gate electrode; an inter-electrode insulating film, in which an interface facing the floating gate electrode and an interface facing a control gate electrode are defined as the first interface and the second interface, respectively; and a control gate electrode. The inter-electrode insulating film includes one or more first elements selected from rare earth elements, one or more second elements selected from Al, Ti, Zr, Hf, Ta, Mg, Ca, Sr and Ba, and oxygen. A composition ratio of the first element, which is defined as the number of atoms of the first element divided by that of the second element, is changed between the first interface and the second interface, and the composition ratio in the vicinity of the first interface is lower than that in the vicinity of the second interface.

摘要翻译： 非易失性半导体存储器件包括：隧道绝缘膜; 浮栅电极; 分别将面对浮置栅极的界面和面对控制栅电极的界面分别定义为第一界面和第二界面的电极间绝缘膜; 和控制栅电极。 电极间绝缘膜包括选自稀土元素，选自Al，Ti，Zr，Hf，Ta，Mg，Ca，Sr和Ba中的一种或多种第二元素和氧的一种或多种第一元素。 被定义为第一元素的原子数除以第二元素的原子数的第一元素的组成比在第一界面和第二界面之间改变，并且第一界面附近的组成比 低于第二界面附近的位置。

公开(公告)号：US20120193597A1

公开(公告)日：2012-08-02

申请号：US13362832

申请日：2012-01-31

申请人： Masao SHINGU ,  Akira Takashima ,  Koichi Muraoka

发明人： Masao SHINGU ,  Akira Takashima ,  Koichi Muraoka

IPC分类号： H01L45/00 ,  H01L27/06 ,  H01L27/24

CPC分类号： H01L45/1273 ,  H01L27/101 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1675

摘要： According to one embodiment, a nonvolatile memory device includes a memory section. The memory section includes a first insulating layer, a second insulating layer and a pair of electrodes. The second insulating layer is formed on and in contact with the first insulating layer. The second insulating layer has at least one of a composition different from a composition of the first insulating layer and a phase state different from a phase state of the first insulating layer. The pair of electrodes is capable of passing a current through a current path along a boundary portion between the first insulating layer and the second insulating layer. An electrical resistance of the current path is changed by a voltage applied between the pair of electrodes.

摘要翻译： 根据一个实施例，非易失性存储器件包括存储器部分。 存储部分包括第一绝缘层，第二绝缘层和一对电极。 第二绝缘层形成在第一绝缘层上并与第一绝缘层接触。 第二绝缘层具有与第一绝缘层的组成不同的组成和与第一绝缘层的相位状态不同的相位状态中的至少一个。 一对电极能够使电流通过沿着第一绝缘层和第二绝缘层之间的边界部分的电流路径。 通过施加在该对电极之间的电压来改变电流路径的电阻。

公开(公告)号：US07804128B2

公开(公告)日：2010-09-28

申请号：US12199036

申请日：2008-08-27

申请人： Keiko Ariyoshi ,  Akira Takashima ,  Shoko Kikuchi ,  Koichi Muraoka

发明人： Keiko Ariyoshi ,  Akira Takashima ,  Shoko Kikuchi ,  Koichi Muraoka

IPC分类号： H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517

摘要： A nonvolatile semiconductor memory device according to an example of the present invention includes a semiconductor region, source/drain areas arranged separately in the semiconductor region, a tunnel insulating film arranged on a channel region between the source/drain areas, a floating gate electrode arranged on the tunnel insulating film, an inter-electrode insulating film arranged on the floating gate electrode, and a control gate electrode arranged on the inter-electrode insulating film. The inter-electrode insulating film includes La, Al and Si.

摘要翻译： 根据本发明实施例的非易失性半导体存储器件包括半导体区域，在半导体区域中单独布置的源极/漏极区域，布置在源极/漏极区域之间的沟道区域上的隧道绝缘膜，布置成 在隧道绝缘膜上，布置在浮栅电极上的电极间绝缘膜和布置在电极间绝缘膜上的控制栅电极。 电极间绝缘膜包括La，Al和Si。

公开(公告)号：US20090242963A1

公开(公告)日：2009-10-01

申请号：US12234197

申请日：2008-09-19

申请人： Masao SHINGU ,  Shoko Kikuchi ,  Akira Takashima ,  Tsunehiro Ino ,  Koichi Muraoka

发明人： Masao SHINGU ,  Shoko Kikuchi ,  Akira Takashima ,  Tsunehiro Ino ,  Koichi Muraoka

IPC分类号： H01L29/792 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66833

摘要： In a semiconductor device, the side walls are made of SiO2, SiN or SiON, and the top insulating film or gate insulating film is made of an oxide including Al, Si, and metal element M so that the number ratio Si/M is set to no less than a number ratio Si/M at a solid solubility limit of SiO2 composition in a composite oxide including metal element M and Al and set to no more than a number ratio Si/M at the condition that the dielectric constant is equal to the dielectric constant of Al2O3 and so that the number ratio Al/M is set to no less than a number ratio Al/M where the crystallization of an oxide of said metal element M is suppressed due to the Al element and set to no more than a number ratio Al/M where the crystallization of the Al2O3 is suppressed due to the metal element M.

摘要翻译： 在半导体器件中，侧壁由SiO 2，SiN或SiON制成，并且顶部绝缘膜或栅极绝缘膜由包括Al，Si和金属元素M的氧化物制成，使得Si / M的数量比设定 在包含金属元素M和Al的复合氧化物中SiO 2组成的固溶度极限的Si / M的数量比不小于Si / M，并且在介电常数等于 Al 2 O 3的介电常数和Al / M的数量比被设定为不小于Al / M的数量比，其中所述金属元素M的氧化物的结晶由于Al元素而被抑制，并且设定为不大于 由于金属元素M而抑制了Al 2 O 3的结晶化的数值比Al / M

公开(公告)号：US08558301B2

公开(公告)日：2013-10-15

申请号：US13208454

申请日：2011-08-12

申请人： Masao Shingu ,  Akira Takashima ,  Koichi Muraoka

发明人： Masao Shingu ,  Akira Takashima ,  Koichi Muraoka

IPC分类号： H01L29/76

CPC分类号： H01L29/788 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/66825

摘要： There is provided a semiconductor device in which degradation of reliability originating in the interface between an upper insulating layer and an element isolation insulating layer is suppressed. The semiconductor device includes: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures. The element isolation insulating layer includes at least one of SiO2, SiN, and SiON, the upper insulating layer is an oxide containing at least one metal M selected from the group consisting of a rare earth metal, Y, Zr, and Hf, and Si, and respective lengths Lcharge, Ltop, and Lgate of the charge storage layer, the upper insulating layer, and the control electrode in a channel length direction satisfy the relation “Lcharge

摘要翻译： 提供一种半导体器件，其中抑制源于上绝缘层和元件隔离绝缘层之间的界面的可靠性的劣化。 半导体器件包括：半导体区域; 多个堆叠结构，其各自设置在所述半导体区域上，并且具有依次堆叠的隧道绝缘膜，电荷存储层，上绝缘层和控制电极; 设置在所述多个堆叠结构的侧面上的元件隔离绝缘层; 以及设置在半导体区域和多个堆叠结构中的源极 - 漏极区域。 元件隔离绝缘层包括SiO 2，SiN和SiON中的至少一种，上绝缘层是含有选自稀土金属，Y，Zr和Hf中的至少一种金属M的氧化物，Si ，并且沟道长度方向上的电荷存储层，上绝缘层和控制电极的各自的长度Lcharge，Ltop和Lgate满足关系“Lcharge

公开(公告)号：US07902588B2

公开(公告)日：2011-03-08

申请号：US11846251

申请日：2007-08-28

申请人： Yukie Nishikawa ,  Akira Takashima ,  Koichi Muraoka

发明人： Yukie Nishikawa ,  Akira Takashima ,  Koichi Muraoka

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42336 ,  H01L29/513

摘要： A nonvolatile semiconductor memory device includes: a tunneling insulating film; a floating gate electrode; an inter-electrode insulating film, in which an interface facing the floating gate electrode and an interface facing a control gate electrode are defined as the first interface and the second interface, respectively; and a control gate electrode. The inter-electrode insulating film includes one or more first elements selected from rare earth elements, one or more second elements selected from Al, Ti, Zr, Hf, Ta, Mg, Ca, Sr and Ba, and oxygen. A composition ratio of the first element, which is defined as the number of atoms of the first element divided by that of the second element, is changed between the first interface and the second interface, and the composition ratio in the vicinity of the first interface is lower than that in the vicinity of the second interface.

摘要翻译： 非易失性半导体存储器件包括：隧道绝缘膜; 浮栅电极; 分别将面对浮置栅极的界面和面对控制栅电极的界面分别定义为第一界面和第二界面的电极间绝缘膜; 和控制栅电极。 电极间绝缘膜包括选自稀土元素，选自Al，Ti，Zr，Hf，Ta，Mg，Ca，Sr和Ba中的一种或多种第二元素和氧的一种或多种第一元素。 被定义为第一元素的原子数除以第二元素的原子数的第一元素的组成比在第一界面和第二界面之间改变，并且第一界面附近的组成比 低于第二界面附近的位置。

公开(公告)号：US07736446B2

公开(公告)日：2010-06-15

申请号：US12051286

申请日：2008-03-19

申请人： Akira Takashima ,  Koichi Muraoka

发明人： Akira Takashima ,  Koichi Muraoka

IPC分类号： C23C16/40

CPC分类号： C23C14/08 ,  C23C14/24 ,  C23C14/50 ,  C23C14/564 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645

摘要： A method for manufacturing a lanthanum oxide compound on a substrate includes: setting the number of H2O molecule, the number of CO molecule and the number of CO2 molecule to one-half or less, one-fifth or less and one-tenth or less per one lanthanum atom, respectively, the H2O molecule, the CO molecule and the CO2 molecule being originated from an H2O gas component, a CO gas component and a CO2 gas component in an atmosphere under manufacture; and supplying a metal raw material containing at least one selected from the group consisting of lanthanum, aluminum, titanium, zirconium and hafnium and an oxygen raw material gas simultaneously for the substrate under the condition that the number of O2 molecule are set to 20 or more per one lanthanum atom, thereby manufacturing the lanthanum oxide compound on the substrate.

摘要翻译： 在基材上制造氧化镧化合物的方法包括：将H 2 O分子的数量，CO分子的数目和CO 2分子的数量设定为每分钟的一半以下，五分之一以下，十分之一以下 一个镧原子分别来自制造气氛中的H 2 O分子，CO分子和CO 2分子源自H 2 O气体组分，CO气体组分和CO 2气体组分; 在氧分子数为20以上的条件下，向基板供给含有选自镧，铝，钛，锆，铪和氧原料气体中的至少一种的金属原料 每一个镧原子，从而在基底上制造氧化镧化合物。