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30 条记录 (耗时 0.019 秒)

    Voltage controlled resonant transmission semiconductor device
    1.
    发明授权
    Voltage controlled resonant transmission semiconductor device 失效
    压控谐振传输半导体器件

    公开(公告)号：US4672423A

    公开(公告)日：1987-06-09

    申请号：US801497

    申请日：1985-11-22

    申请人： Alan B. Fowler ,  Allan M. Hartstein

    发明人： Alan B. Fowler ,  Allan M. Hartstein

    IPC分类号： H01L29/66 ,  H01L29/78

    CPC分类号： B82Y10/00 ,  H01L29/66977

    摘要： In a transistor structure a buried gate positioned in the layer above a conduction channel and below a broad gate which overlaps the source and drain, when the voltages applied to the buried gate and the overlapping gate are varied independently, a potential well between two barriers can be established which permits conduction by the physical mechanism of resonant transmission. The potential well between two barriers required for the resonant transmission mechanism is achieved in one structure by a buried gate under an overlapping gate with both width and separation dimension control and in a second structure using split-buried gate under an overlapping gate that is embossed in the region of the split gate. With gate and separation dimensions of the order of 1000 .ANG. switching speeds of the order of 10.sup.-12 seconds are achieved.

    摘要翻译： 在晶体管结构中，当施加到掩埋栅极和重叠栅极的电压独立地变化时，位于导电沟道上方并且在与栅极和漏极重叠的宽栅极之下的层中的掩埋栅极，两个势垒之间的势阱可以 可以通过谐振传输的物理机制进行导通。 谐振传输机构所需的两个障碍之间的潜在井在一个结构中通过在具有宽度和间隔尺寸控制的重叠栅极下的掩埋栅极实现，并且在第二结构中使用在重叠栅极下方的分裂掩埋栅极被压印 分裂门的区域。 具有门极和分离尺寸为1000安培开关速度的量级为10-12秒。

    Micromechanical display logic and array
    5.
    发明授权
    Micromechanical display logic and array 失效
    微机械显示逻辑和阵列

    公开(公告)号：US4229732A

    公开(公告)日：1980-10-21

    申请号：US968054

    申请日：1978-12-11

    申请人： Allan M. Hartstein ,  Kurt E. Petersen

    发明人： Allan M. Hartstein ,  Kurt E. Petersen

    IPC分类号： H04N5/74 ,  G02B27/50 ,  G02F1/19 ,  G09F9/37 ,  H01H59/00 ,  G08B5/24

    CPC分类号： G02B26/0833 ,  G09F9/372 ,  H01H59/0009 ,  Y10T29/49002

    摘要： A display device, addressing circuitry, and semiconductor control logic are all portions of an integrated structure formed by thin film technology on a single silicon wafer. The display comprises a thin film micromechanical electrostatic form of light reflective display formed by depositing thin films upon a silicon wafer and selectively etching to form metal-amorphous oxide micromechanical leaves deflected by applying potential thereto to provide electrostatic deflection. MOSFET devices are also formed upon the silicon wafer in juxtaposition with a plurality of micromechanical display elements. Addressing circuitry is connected to the MOSFET devices.

    摘要翻译： 显示装置，寻址电路和半导体控制逻辑都是在单个硅晶片上由薄膜技术形成的集成结构的部分。 显示器包括薄膜微机械静电形式的光反射显示器，其通过在硅晶片上沉积薄膜并选择性地蚀刻以形成通过施加电位而偏转以提供静电偏转的金属非晶氧化物微机械叶片。 MOSFET器件也与多个微机械显示元件并置在硅晶片上。 寻址电路连接到MOSFET器件。

    Method and apparatus for prefetching branch history information
    8.
    发明授权
    Method and apparatus for prefetching branch history information 失效
    用于预取分支历史信息的方法和装置

    公开(公告)号：US07493480B2

    公开(公告)日：2009-02-17

    申请号：US10197714

    申请日：2002-07-18

    申请人： Philip G. Emma ,  Klaus J. Getzlaff ,  Allan M. Hartstein ,  Thomas Pflueger ,  Thomas R. Puzak ,  Eric Mark Schwarz ,  Vijayalakshmi Srinivasan

    发明人： Philip G. Emma ,  Klaus J. Getzlaff ,  Allan M. Hartstein ,  Thomas Pflueger ,  Thomas R. Puzak ,  Eric Mark Schwarz ,  Vijayalakshmi Srinivasan

    IPC分类号： G06F9/00

    CPC分类号： G06F9/3806

    摘要： A two level branch history table (TLBHT) is substantially improved by providing a mechanism to prefetch entries from the very large second level branch history table (L2 BHT) into the active (very fast) first level branch history table (L1 BHT) before the processor uses them in the branch prediction process and at the same time prefetch cache misses into the instruction cache. The mechanism prefetches entries from the very large L2 BHT into the very fast L1 BHT before the processor uses them in the branch prediction process. A TLBHT is successful because it can prefetch branch entries into the L1 BHT sufficiently ahead of the time the entry is needed. This feature of the TLBHT is also used to prefetch instructions into the cache ahead of their use. In fact, the timeliness of the prefetches produced by the TLBHT can be used to remove most of the cycle time penalty incurred by cache misses.

    摘要翻译： 通过提供一种将超大型第二级分支历史表（L2 BHT）中的条目预取到活动（非常快）的第一级分支历史表（L1 BHT）中的条目之前，两级分支历史表（TLBHT）被大大改善 处理器在分支预测过程中使用它们，并且同时将高速缓存未命中预取到指令高速缓存中。 在处理器在分支预测过程中使用它们之前，该机制将从非常大的L2 BHT中将条目预取到非常快的L1 BHT中。 TLBHT是成功的，因为它可以在需要输入的时间之前将分支条目预取到L1 BHT中。 TLBHT的这个功能也用于在使用之前将指令预取到高速缓存中。 实际上，由TLBHT产生的预取的及时性可以用来消除高速缓存未命中引起的大部分周期时间损失。

    3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS TO ENABLE RELIABLE OPERATION OF PROCESSORS AT SPEEDS ABOVE SPECIFIED LIMITS
    10.
    发明申请
    3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS TO ENABLE RELIABLE OPERATION OF PROCESSORS AT SPEEDS ABOVE SPECIFIED LIMITS 有权
    3-D堆叠式多处理器结构和方法，使加工程序的可靠运行速度超过指定的限制

    公开(公告)号：US20140006750A1

    公开(公告)日：2014-01-02

    申请号：US13602777

    申请日：2012-09-04

    申请人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan K. Kailas

    发明人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan K. Kailas

    IPC分类号： G06F15/76

    CPC分类号： G06F15/7832 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/24

    摘要： A three-dimensional (3-D) processor system includes a first processor chip and a second processor chip in a stacked configuration. The first processor chip includes a first processor having a first set of state registers. The second processor chip includes a second processor having a second set of state registers that corresponds to the first set of state registers. The first and second processors are connected through vertical connections between the first and second processor chips. A mode control circuit operates the processor system in one of a plurality of operating modes. In one mode of operation, the first processor is active and the second processor is inactive, and the first processor operates at a speed greater than a maximum safe speed of the first processor, and the first processor uses the second set of state registers of the second processor to checkpoint a state of the first processor.

    摘要翻译： 三维（3-D）处理器系统包括堆叠配置的第一处理器芯片和第二处理器芯片。 第一处理器芯片包括具有第一组状态寄存器的第一处理器。 第二处理器芯片包括具有对应于第一组状态寄存器的第二组状态寄存器的第二处理器。 第一和第二处理器通过第一和第二处理器芯片之间的垂直连接连接。 模式控制电路以多种操作模式之一操作处理器系统。 在一种操作模式中，第一处理器是有效的，而第二处理器是不活动的，并且第一处理器以大于第一处理器的最大安全速度的速度操作，并且第一处理器使用第二处理器的第二组状态寄存器 第二处理器来检查第一处理器的状态。