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1.发明授权Method for improved triggering and oscillation suppression of ESD clamping devices 失效改善ESD钳位装置触发和振荡抑制的方法公开(公告)号：US07646573B2
公开(公告)日：2010-01-12
申请号：US12133424
申请日：2008-06-05
CPC分类号： H01L27/0266
摘要： An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) includes an RC trigger device configured between a pair of power rails, a first control path coupled to the RC trigger device, and a second control path coupled to the RC trigger device. A power clamp is configured between the power rails for discharging current from an ESD event, the power clamp having an input coupled to outputs of the first and second control paths, the power clamp independently controllable by the first and second control paths. The first and second control paths are further configured to prevent the power clamp from reactivating following an initial deactivation of the power clamp.
摘要翻译： 用于保护集成电路免受静电放电（ESD）的装置包括RC触发装置，其配置在耦合到RC触发装置的一对电源轨，第一控制路径和耦合到RC触发装置的第二控制路径之间。 功率钳被配置在用于从ESD事件放电的电源轨之间，功率钳具有耦合到第一和第二控制路径的输出的输入，功率钳由第一和第二控制路径独立地控制。 第一和第二控制路径还被配置为防止在电源钳的初始去激活之后电源钳位被重新激活。
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2.发明授权Apparatus and method for improved triggering and oscillation suppression of ESD clamping devices 失效用于改善ESD钳位装置的触发和振荡抑制的装置和方法公开(公告)号：US07397641B2
公开(公告)日：2008-07-08
申请号：US11276411
申请日：2006-02-28
CPC分类号： H01L27/0266
摘要： An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) includes an RC trigger device configured between a pair of power rails, a first control path coupled to the RC trigger device, and a second control path coupled to the RC trigger device. A power clamp is configured between the power rails for discharging current from an ESD event, the power clamp having an input coupled to outputs of the first and second control paths, the power clamp independently controllable by the first and second control paths. The first and second control paths are further configured to prevent the power clamp from reactivating following an initial deactivation of the power clamp.
摘要翻译： 用于保护集成电路免受静电放电（ESD）的装置包括RC触发装置，其配置在耦合到RC触发装置的一对电源轨，第一控制路径和耦合到RC触发装置的第二控制路径之间。 功率钳被配置在用于从ESD事件放电的电源轨之间，功率钳具有耦合到第一和第二控制路径的输出的输入，功率钳由第一和第二控制路径独立地控制。 第一和第二控制路径还被配置为防止在电源钳的初始去激活之后电源钳位被重新激活。
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3.发明申请METHOD FOR IMPROVED TRIGGERING AND OSCILLATION SUPRESSION OF ESD CLAMPING DEVICES 失效用于改善ESD钳位装置的触发和振荡抑制的方法公开(公告)号：US20080232012A1
公开(公告)日：2008-09-25
申请号：US12133424
申请日：2008-06-05
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) includes an RC trigger device configured between a pair of power rails, a first control path coupled to the RC trigger device, and a second control path coupled to the RC trigger device. A power clamp is configured between the power rails for discharging current from an ESD event, the power clamp having an input coupled to outputs of the first and second control paths, the power clamp independently controllable by the first and second control paths. The first and second control paths are further configured to prevent the power clamp from reactivating following an initial deactivation of the power clamp.
摘要翻译： 用于保护集成电路免受静电放电（ESD）的装置包括RC触发装置，其配置在耦合到RC触发装置的一对电源轨，第一控制路径和耦合到RC触发装置的第二控制路径之间。 功率钳被配置在用于从ESD事件放电的电源轨之间，功率钳具有耦合到第一和第二控制路径的输出的输入，功率钳由第一和第二控制路径独立地控制。 第一和第二控制路径还被配置为防止在电源钳的初始去激活之后电源钳位被重新激活。
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公开(公告)号：US08839054B2
公开(公告)日：2014-09-16
申请号：US13445187
申请日：2012-04-12
申请人： George M. Braceras , Albert M. Chu , Kevin W. Gorman , Michael R. Ouellette , Ronald A. Piro , Daryl M. Seitzer , Rohit Shetty , Thomas W. Wyckoff
发明人： George M. Braceras , Albert M. Chu , Kevin W. Gorman , Michael R. Ouellette , Ronald A. Piro , Daryl M. Seitzer , Rohit Shetty , Thomas W. Wyckoff
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G06F11/0793 , G11C17/00 , G11C29/4401 , G11C29/822
摘要： A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.
摘要翻译： 提供了具有冗余性和使用方法的只读存储器（ROM）。 具有冗余的ROM包括耦合到具有一个或多个冗余修复的修复电路的可编程阵列。 一个或多个冗余修复包括字地址匹配逻辑块，数据I / O地址和三态缓冲器。 字地址匹配逻辑块作为控制输入提供给三态缓冲器，并且将数据I / O地址作为输入提供给三态缓冲器。 提供每个冗余修复的三态缓冲器的输出作为一个或多个逻辑器件的第一输入。 提供ROM位单元阵列的一个或多个数据输出作为一个或多个逻辑器件中的相应一个的第二输入。
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公开(公告)号：US20130211749A1
公开(公告)日：2013-08-15
申请号：US13396775
申请日：2012-02-15
IPC分类号： G01R31/308 , G06F19/00
CPC分类号： G01R31/311
摘要： A semiconductor device structure is embedded within a semiconductor chip that calibrates a photon-emission luminosity scale by running multiple known currents through the device. The method comprises embedding at least one photon emission device in an integrated circuit having at least one functional device. A control current is applied to the at least one photon emission device. The photon emission intensity produced by the at least one photon emission device is captured. The current density of the at least one photon emission device is calculated. A test current is applied to the at least one functional device. The photon emission intensity produced by the at least one functional device is captured. The current density of the at least one functional device is estimated based on a comparison with the calculated current density of the at least one photon emission device.
摘要翻译： 半导体器件结构嵌入半导体芯片内，通过运行多个已知电流通过器件来校准光子发射光度标度。 该方法包括将至少一个光子发射装置嵌入到具有至少一个功能装置的集成电路中。 控制电流被施加到至少一个光子发射装置。 捕获由至少一个光子发射装置产生的光子发射强度。 计算出至少一个光子发射装置的电流密度。 测试电流被施加到所述至少一个功能装置。 捕获由至少一个功能装置产生的光子发射强度。 基于与计算出的至少一个光子发射装置的电流密度的比较来估计至少一个功能装置的电流密度。
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公开(公告)号：US09052356B2
公开(公告)日：2015-06-09
申请号：US13396775
申请日：2012-02-15
IPC分类号： G01R31/00 , G01R31/311
CPC分类号： G01R31/311
摘要： A semiconductor device structure is embedded within a semiconductor chip that calibrates a photon-emission luminosity scale by running multiple known currents through the device. The method comprises embedding at least one photon emission device in an integrated circuit having at least one functional device. A control current is applied to the at least one photon emission device. The photon emission intensity produced by the at least one photon emission device is captured. The current density of the at least one photon emission device is calculated. A test current is applied to the at least one functional device. The photon emission intensity produced by the at least one functional device is captured. The current density of the at least one functional device is estimated based on a comparison with the calculated current density of the at least one photon emission device.
摘要翻译： 半导体器件结构嵌入半导体芯片内，通过运行多个已知电流通过器件来校准光子发射光度标度。 该方法包括将至少一个光子发射装置嵌入到具有至少一个功能装置的集成电路中。 控制电流被施加到至少一个光子发射装置。 捕获由至少一个光子发射装置产生的光子发射强度。 计算出至少一个光子发射装置的电流密度。 测试电流被施加到所述至少一个功能装置。 捕获由至少一个功能装置产生的光子发射强度。 基于与计算出的至少一个光子发射装置的电流密度的比较来估计至少一个功能装置的电流密度。
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7.发明授权Systems and methods for determining adjustable wafer acceptance criteria based on chip characteristics 有权基于芯片特性确定可调晶片接收标准的系统和方法公开(公告)号：US08862417B2
公开(公告)日：2014-10-14
申请号：US13151337
申请日：2011-06-02
CPC分类号： H01L22/20 , H01L22/12 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： Systems and methods for determining adjustable wafer acceptance criteria based on chip characteristics. The method includes measuring a density of at least one chip. The method further includes computing a difference in density between the density of the at least one chip and a density of at least one kerf structure. The method further includes calculating an offset value to modify a Wafer Acceptance Criteria (WAC) to match the density difference between the at least one chip and the at least one kerf structure. The method further includes applying the offset value to the WAC for a wafer level measurement in order to increase chip yield performance.
摘要翻译： 基于芯片特性确定可调晶片接收标准的系统和方法。 该方法包括测量至少一个芯片的密度。 该方法还包括计算至少一个芯片的密度与至少一个切口结构的密度之间的密度差。 该方法还包括计算偏移值以修改晶片验收标准（WAC）以匹配至少一个芯片和至少一个切口结构之间的密度差。 该方法还包括将偏移值应用于晶片级测量的WAC以提高芯片产量性能。
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公开(公告)号：US08519772B2
公开(公告)日：2013-08-27
申请号：US13075652
申请日：2011-03-30
IPC分类号： H03K17/687
CPC分类号： H03K19/0016
摘要： Structures and methods for implementing alternating power gating in integrated circuits. A semiconductor structure includes a power gated circuit including a group of power gate switches and an alternating enable generator that generates enabling signals. Each respective one of the power gate switches is enabled by a respective one of the enabling signals. The alternating generator generates the enabling signals such that a first enabled power gate switch is alternated amongst the group of power gate switches.
摘要翻译： 在集成电路中实现交流电源门控的结构和方法。 半导体结构包括电源门控电路，其包括一组电源门开关和产生使能信号的交替使能发生器。 每个相应的一个功率门开关由使能信号中的相应一个使能。 交替发电机产生使能信号，使得第一使能电源门极开关在一组电源门开关之间交替。
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9.发明申请CONTENT ADDRESSABLE MEMORY WITH HIDDEN TABLE UPDATE, DESIGN STRUCTURE AND METHOD 审中-公开内容可寻址存储器，具有隐藏表更新，设计结构和方法公开(公告)号：US20090240875A1
公开(公告)日：2009-09-24
申请号：US12050340
申请日：2008-03-18
申请人： Albert M. Chu , Paul C. Parries , Daryl M. Seitzer
发明人： Albert M. Chu , Paul C. Parries , Daryl M. Seitzer
CPC分类号： G11C15/043 , G11C11/406
摘要： Disclosed are embodiments of memory circuit having two discrete memory devices with two discrete memory arrays that store essentially identical data banks. The first device is a conventional memory adapted to perform all maintenance operations that require read functions (i.e., all update and refresh operations). The second device is a DRAM-based CAM device adapted to perform parallel search and overwrite operations only. Performance of overwrite operations by the second device occurs in conjunction with performance of maintenance operations by the first device so that corresponding memory cells in the two devices store essentially identical data values. Since the data banks in the memory devices are essentially identical and since maintenance and parallel search operations are not performed by the same device, the parallel search operations can be performed without interruption. Also disclosed are embodiments of an associated design structure and method.
摘要翻译： 公开了具有两个分立存储器件的存储器电路的实施例，其具有存储基本上相同的数据库的两个分立存储器阵列。 第一设备是适于执行需要读取功能（即，所有更新和刷新操作）的所有维护操作的常规存储器。 第二设备是仅适用于执行并行搜索和重写操作的基于DRAM的CAM设备。 第二设备的覆盖操作的性能与第一设备的维护操作的性能一起发生，使得两个设备中的相应存储器单元存储基本上相同的数据值。 由于存储器件中的数据库基本上相同，并且由于维护和并行搜索操作不由同一设备执行，所以可以不中断地执行并行搜索操作。 还公开了相关设计结构和方法的实施例。
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公开(公告)号：US07503020B2
公开(公告)日：2009-03-10
申请号：US11424922
申请日：2006-06-19
申请人： Robert J. Allen , Faye D. Baker , Albert M. Chu , Michael S. Gray , Jason Hibbeler , Daniel N. Maynard , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Faye D. Baker , Albert M. Chu , Michael S. Gray , Jason Hibbeler , Daniel N. Maynard , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.
摘要翻译： 一种用于优化集成电路设计以提高制造产量的方法和服务。 本发明使用制造数据和算法来识别故障概率高的区域，即关键区域。 本发明进一步改变电路设计的布局以减少临界面积，从而降低在制造过程中发生故障的可能性。 确定关键区域的方法包括通用运行，几何映射和Voronoi图。 优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。
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