公开(公告)号：US07440030B2

公开(公告)日：2008-10-21

申请号：US10247044

申请日：2002-09-19

Applicant: Alexander G. MacInnis ,  Sheng Zhong ,  Jose R. Alvarez

Inventor： Alexander G. MacInnis ,  Sheng Zhong ,  Jose R. Alvarez

IPC: H04N7/01

CPC classification number: H04N7/012 ,  H04N19/523

Abstract: A method is provided for displaying progressive video content on an interlaced display device. The method comprises vertically phase shifting video lines of the progressive video content to correctly position the video lines with respect to a video field of the interlaced display device. The method further comprises scaling the video lines of progressive video content to match a vertical size of a video field of the interlaced display device.

Abstract translation: 提供一种用于在隔行显示装置上显示逐行视频内容的方法。 该方法包括垂直相移逐行视频内容的视频行，以相对于隔行显示装置的视频场正确定位视频行。 该方法还包括缩放逐行视频内容的视频行以匹配隔行显示设备的视频场的垂直尺寸。

公开(公告)号：US08229002B2

公开(公告)日：2012-07-24

申请号：US13018840

申请日：2011-02-01

Applicant: Alexander G. MacInnis ,  Jose R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

Inventor： Alexander G. MacInnis ,  Jose R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

IPC: H04N7/18

CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90 ,  H04N19/91

Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

公开(公告)号：US20120020412A1

公开(公告)日：2012-01-26

申请号：US13205776

申请日：2011-08-09

Applicant: Jose R. Alvarez ,  Alexander G. MacInnis ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

Inventor： Jose R. Alvarez ,  Alexander G. MacInnis ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

IPC: H04N7/30 ,  H04N7/26

CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/13 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90

Abstract: A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel. The variable-length decoders operate as part of a pipeline wherein the variable-length decoders alternate, stage-by-stage, decoding macroblocks.

Abstract translation: 一种用于解码数字视频数据流的系统和方法。 在一个方面，多个硬件加速模块与核心处理器一起使用。 加速器在解码管线中操作，其中在任何给定阶段，每个加速器对视频数据的特定宏块进行操作。 在随后的流水线阶段，每个加速器对数据流中的下一个宏块进行工作，该前一阶段的另一个加速器工作。 核心处理器在每个阶段轮询所有加速器。 当所有加速器在给定阶​​段完成任务时，核心处理器启动下一阶段。 在另一方面，采用两个可变长度解码器来同时解码视频帧的两个宏块行。 每个可变长度解码器用于对分配的行进行解码，并行并行地进行可变长度解码。 可变长度解码器作为流水线的一部分进行操作，其中可变长度解码器逐级交替解码宏块。

公开(公告)号：US09104424B2

公开(公告)日：2015-08-11

申请号：US13205776

申请日：2011-08-09

Applicant: Jose R. Alvarez ,  Alexander G. MacInnis ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

Inventor： Jose R. Alvarez ,  Alexander G. MacInnis ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

IPC: H04N7/18 ,  G06F9/38 ,  H04N19/176 ,  H04N19/70 ,  H04N19/13 ,  H04N19/122 ,  H04N19/129 ,  H04N19/61 ,  H04N19/60 ,  H04N19/12 ,  H04N19/157 ,  H04N19/44 ,  H04N19/82 ,  H04N19/423 ,  H04N19/90

CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/13 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90

Abstract: A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel. The variable-length decoders operate as part of a pipeline wherein the variable-length decoders alternate, stage-by-stage, decoding macroblocks.

公开(公告)号：US20110122941A1

公开(公告)日：2011-05-26

申请号：US13018840

申请日：2011-02-01

Applicant: Alexander G. MacInnis ,  Jose R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

Inventor： Alexander G. MacInnis ,  Jose R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

IPC: H04N7/26 ,  H04N7/30

CPC classification number: G06F9/3861 ,  G06F9/3877 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90 ,  H04N19/91

Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

Abstract translation: 用于解码数字视频数据的系统和方法。 解码系统采用辅助核心处理器执行所选解码任务的硬件加速器。 硬件加速器可配置为支持多种现有和将来的编码/解码格式。 加速器可配置为支持落入基于DCT的熵解码的块运动补偿压缩算法的一般类别中的任何现有或将来的编码/解码格式。 硬件加速器示例性地包括可编程熵解码器，逆量化模块，反相离散余弦变换模块，像素滤波器，运动补偿模块和去块滤波器。 硬件加速器在解码流水线中起作用，其中在流水线中的任何给定阶段，在给定宏块上执行给定功能的同时，数据流中的下一个宏块正在通过管道中的先前功能进行处理。

公开(公告)号：US07440504B2

公开(公告)日：2008-10-21

申请号：US10246977

申请日：2002-09-19

Applicant: Alexander G. Maclnnis ,  Sheng Zhong ,  Jose R. Alvarez

Inventor： Alexander G. Maclnnis ,  Sheng Zhong ,  Jose R. Alvarez

IPC: H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04B1/66

CPC classification number: H04N19/86 ,  H04N19/117 ,  H04N19/159 ,  H04N19/16 ,  H04N19/176 ,  H04N19/80

Abstract: A method and apparatus are disclosed for adaptively selecting a deblocking filter used in video de-blocking. Determinations are made as to whether each of a set of spatially adjacent video blocks is inter-coded or intra-coded and whether each of said adjacent video blocks is field-coded or frame-coded. A deblocking filter is selected (an interlace deblocking filter or a frame deblocking filter) based on the determinations. The selected deblocking filter is used to filter across a boundary between adjacent video blocks.

Abstract translation: 公开了一种用于自适应地选择用于视频去阻塞中的去块滤波器的方法和装置。 确定一组空间相邻的视频块中的每一个是帧间编码还是帧内编码，以及所述相邻视频块中的每一个是场编码还是帧编码。 基于确定，选择去块滤波器（隔行去块滤波器或帧去块滤波器）。 所选择的去块滤波器用于过滤相邻视频块之间的边界。

公开(公告)号：US08441562B1

公开(公告)日：2013-05-14

申请号：US12875077

申请日：2010-09-02

Applicant: Gabor Szedo ,  Jose R. Alvarez

Inventor： Gabor Szedo ,  Jose R. Alvarez

IPC: H04N5/335

CPC classification number: H04N17/002 ,  H04N9/045

Abstract: In one embodiment of the present invention, a method for determining a phase alignment of a Bayer color filter array is provided. A quincunx lattice of the color filter array corresponding to a first color component is determined from an input frame of image data. Elements of the color filter array corresponding to first and second rectangular lattices of the color filter array are selected. Second and third color components corresponding to elements of the first and second rectangular lattices are determined from the sample values in an input frame of image data.

Abstract translation: 在本发明的一个实施例中，提供了一种用于确定拜耳滤色器阵列的相位对准的方法。 从图像数据的输入帧确定与第一颜色分量相对应的滤色器阵列的五点阵。 选择与滤色器阵列的第一和第二矩形格子相对应的滤色器阵列的元件。 从图像数据的输入帧中的样本值确定与第一和第二矩形格子的元素对应的第二和第三颜色成分。

公开(公告)号：US08149909B1

公开(公告)日：2012-04-03

申请号：US11249213

申请日：2005-10-13

Applicant: Ilie Garbacea ,  Lulin Chen ,  Jose R. Alvarez

Inventor： Ilie Garbacea ,  Lulin Chen ,  Jose R. Alvarez

IPC: H04N7/12 ,  H04N11/04

CPC classification number: H04N19/00096 ,  H04N19/126 ,  H04N19/14 ,  H04N19/176

Abstract: In some embodiments, macroblock-level encoding parameters are assigned to weighted Linear combinations of corresponding content-category-level encoding parameters. A macroblock quantization parameter (QP) modulation is set to a weighted linear combination of content category QP modulations. Content categories may identify potentially overlapping content types. The combination weights may be similarity measures describing macroblock similarities to content categories. A macroblock may be associated with multiple content categories, with different similarity levels for different content categories. A similarity measure for a given macroblock with respect to a content category may be defined as a number (between 0 and 8) of neighboring macroblocks that meet a similarity condition, provided the macroblock meets a qualification condition. The similarity condition may be computationally simpler than the qualification condition. Content-category-level statistics are generated by combining block-level statistics. Content-category-level statistics may be used in encoding subsequent frames.

Abstract translation: 在一些实施例中，宏块级编码参数被分配给相应内容类别级编码参数的加权线性组合。 宏块量化参数（QP）调制被设置为内容类别QP调制的加权线性组合。 内容类别可能会识别可能重叠的内容类型。 组合权重可以是描述与内容类别的宏块相似性的相似性度量。 宏块可以与多个内容类别相关联，具有针对不同内容类别的不同相似度级别。 如果宏块符合资格条件，则相对于内容类别的给定宏块的相似性度量可以被定义为满足相似性条件的相邻宏块之间的数目（在0和8之间）。 相似性条件可能比资格条件计算简单。 通过组合块级统计信息生成内容类别级统计信息。 内容类别级统计可用于对后续帧进行编码。

公开(公告)号：US08126283B1

公开(公告)日：2012-02-28

申请号：US11250102

申请日：2005-10-13

Applicant: Ilie Garbacea ,  Lulin Chen ,  Jose R. Alvarez

Inventor： Ilie Garbacea ,  Lulin Chen ,  Jose R. Alvarez

IPC: G06K9/46

CPC classification number: G06F17/30831 ,  G06F17/3079 ,  H04N19/124 ,  H04N19/136 ,  H04N19/142 ,  H04N19/147 ,  H04N19/149 ,  H04N19/176 ,  H04N19/196 ,  H04N19/85

Abstract: In some embodiments, content-category-level encoding statistical indicators (statistics) are assigned to weighted linear combinations of corresponding macroblock-level statistics. Content categories may identify potentially overlapping content types such as sky, water, grass, skin, and red content. The combination weights may be similarity measures describing macroblock similarities to content categories. A given macroblock may be associated with multiple content categories, with different similarity levels for different content categories. A similarity measure for a given macroblock with respect to a content category may be defined as a number (between 0 and 8) of neighboring macroblocks that meet a similarity condition, provided the macroblock meets a qualification condition. The similarity condition may be computationally simpler than the qualification condition. Macroblock-level encoding parameters are generated by combining content-category-level parameters.

Abstract translation: 在一些实施例中，内容类别级编码统计指标（统计）被分配给相应宏块级统计的加权线性组合。 内容类别可能会识别潜在重叠的内容类型，如天空，水，草，皮肤和红色内容。 组合权重可以是描述与内容类别的宏块相似性的相似性度量。 给定宏块可以与多个内容类别相关联，具有针对不同内容类别的不同相似度级别。 如果宏块符合资格条件，则相对于内容类别的给定宏块的相似性度量可以被定义为满足相似性条件的相邻宏块之间的数目（在0和8之间）。 相似性条件可能比资格条件计算简单。 通过组合内容类别级参数来生成宏块级编码参数。

公开(公告)号：US20110090364A1

公开(公告)日：2011-04-21

申请号：US12979550

申请日：2010-12-28

Applicant: Jose R. Alvarez ,  Guy Cote

Inventor： Jose R. Alvarez ,  Guy Cote

IPC: H04N5/225

CPC classification number: H04N19/59 ,  H04N19/117 ,  H04N19/124 ,  H04N19/132 ,  H04N19/14 ,  H04N19/146 ,  H04N19/17 ,  H04N19/176 ,  H04N19/61 ,  H04N19/85

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to perform image signal processing using encoding related information. The second circuit may be configured to encode image data using image signal processing related information, wherein said first circuit is further configured to pass said image signal processing related information to said second circuit and said second circuit is further configured to pass said encoding related information to said first circuit.

Abstract translation: 一种包括第一电路和第二电路的装置。 第一电路可以被配置为使用编码相关信息来执行图像信号处理。 第二电路可以被配置为使用图像信号处理相关信息对图像数据进行编码，其中所述第一电路还被配置为将所述图像信号处理相关信息传递到所述第二电路，并且所述第二电路还被配置为将所述编码相关信息传递到 说第一个电路。