公开(公告)号：US20130019037A1

公开(公告)日：2013-01-17

申请号：US13184384

申请日：2011-07-15

申请人： Allan Flippin ,  William Densham ,  Jiun Heng Goh ,  Constantin Bucur ,  Flavius Lupu ,  Stefan Maireanu

发明人： Allan Flippin ,  William Densham ,  Jiun Heng Goh ,  Constantin Bucur ,  Flavius Lupu ,  Stefan Maireanu

IPC分类号： G06F13/42 ,  G06F11/30 ,  G06F1/26

CPC分类号： H01M10/425 ,  H02J7/0021

摘要： A battery management chip may include a battery management unit and a vertical bus circuit. The battery management unit can monitor a cell status of multiple cells in a battery module coupled to the battery management chip in response to an instruction from a host processor. The vertical bus circuit may transfer the instruction from the host processor to the battery management unit. The vertical bus circuit may include a first receiver, a command processor and a first transmitter. The first receiver can receive a first pair of differential input data signals. The command processor can process the first pair of differential input data signals. The first transmitter can output a first pair of differential output data signals.

摘要翻译： 电池管理芯片可以包括电池管理单元和垂直总线电路。 电池管理单元可以响应于来自主处理器的指令来监视耦合到电池管理芯片的电池模块中的多个单元的单元状态。 垂直总线电路可以将指令从主处理器传送到电池管理单元。 垂直总线电路可以包括第一接收器，命令处理器和第一发射器。 第一接收机可以接收第一对差分输入数据信号。 命令处理器可以处理第一对差分输入数据信号。 第一发射机可以输出第一对差分输出数据信号。

公开(公告)号：US08907625B2

公开(公告)日：2014-12-09

申请号：US13184384

申请日：2011-07-15

申请人： Allan Flippin ,  William Densham ,  Jiun Heng Goh ,  Constantin Bucur ,  Flavius Lupu ,  Stefan Maireanu

发明人： Allan Flippin ,  William Densham ,  Jiun Heng Goh ,  Constantin Bucur ,  Flavius Lupu ,  Stefan Maireanu

IPC分类号： H01M10/44 ,  H01M10/46 ,  H01M10/42 ,  H02J7/00

CPC分类号： H01M10/425 ,  H02J7/0021

摘要： A battery management chip may include a battery management unit and a vertical bus circuit. The battery management unit can monitor a cell status of multiple cells in a battery module coupled to the battery management chip in response to an instruction from a host processor. The vertical bus circuit may transfer the instruction from the host processor to the battery management unit. The vertical bus circuit may include a first receiver, a command processor and a first transmitter. The first receiver can receive a first pair of differential input data signals. The command processor can process the first pair of differential input data signals. The first transmitter can output a first pair of differential output data signals.

摘要翻译： 电池管理芯片可以包括电池管理单元和垂直总线电路。 电池管理单元可以响应于来自主处理器的指令来监视耦合到电池管理芯片的电池模块中的多个单元的单元状态。 垂直总线电路可以将指令从主处理器传送到电池管理单元。 垂直总线电路可以包括第一接收器，命令处理器和第一发射器。 第一接收机可以接收第一对差分输入数据信号。 命令处理器可以处理第一对差分输入数据信号。 第一发射机可以输出第一对差分输出数据信号。

公开(公告)号：US08612733B2

公开(公告)日：2013-12-17

申请号：US13184405

申请日：2011-07-15

申请人： Allan Flippin

发明人： Allan Flippin

IPC分类号： G06F3/00 ,  G06F15/177

CPC分类号： H01M10/425 ,  H02J7/0021

摘要： A system may include multiple chips and a host processor. The host processor can be coupled to the multiple chips and send an enumerate command. The multiple chips can propagate an enumerate packet including the enumerate command from chip-to-chip, and each chip can use information in the enumerate packet to determine its own unique address.

摘要翻译： 系统可以包括多个芯片和主机处理器。 主处理器可以耦合到多个芯片并发送枚举命令。 多个芯片可以从芯片到芯片传播包括枚举命令的枚举分组，并且每个芯片可以使用枚举分组中的信息来确定其自己的唯一地址。

公开(公告)号：US07017020B2

公开(公告)日：2006-03-21

申请号：US10740641

申请日：2003-12-22

申请人： Joseph Herbst ,  Allan Flippin

发明人： Joseph Herbst ,  Allan Flippin

IPC分类号： G06F13/00

CPC分类号： H04L12/56 ,  H04L69/16 ,  H04Q11/0478

摘要： A method and apparatus for optimizing access to memory, wherein the method includes the steps of receiving a first request for access to a memory, receiving at least two additional requests for access to the memory, and determining a first clock overhead associated with the first request for access to the memory. The method further includes the steps of determining an additional clock overhead associated with each of the at least two additional requests for access to the memory in conjunction with the first request, determining a combination of requests that can be processed together using an optimized overhead, and processing the combination of requests as a single request with the optimal overhead.

摘要翻译： 一种用于优化对存储器的访问的方法和装置，其中所述方法包括以下步骤：接收访问存储器的第一请求，接收至少两个对所述存储器的访问的附加请求，以及确定与所述第一请求相关联的第一时钟开销 用于访问内存。 所述方法还包括以下步骤：结合所述第一请求确定与所述至少两个附加请求中的至少两个附加请求相关联的附加时钟开销，确定可以使用优化的开销一起处理的请求的组合;以及 将请求的组合作为具有最佳开销的单个请求来处理。

公开(公告)号：US06735679B1

公开(公告)日：2004-05-11

申请号：US09599525

申请日：2000-06-23

申请人： Joseph Herbst ,  Allan Flippin

发明人： Joseph Herbst ,  Allan Flippin

IPC分类号： G06F1300

CPC分类号： H04L47/2408 ,  H04L12/18 ,  H04L12/42 ,  H04L12/46 ,  H04L12/4625 ,  H04L12/56 ,  H04L12/5601 ,  H04L12/5602 ,  H04L29/06 ,  H04L45/00 ,  H04L45/24 ,  H04L45/245 ,  H04L45/742 ,  H04L47/10 ,  H04L47/125 ,  H04L47/2441 ,  H04L47/2458 ,  H04L47/50 ,  H04L47/6215 ,  H04L47/623 ,  H04L47/745 ,  H04L47/827 ,  H04L49/102 ,  H04L49/103 ,  H04L49/109 ,  H04L49/25 ,  H04L49/3072 ,  H04L49/3081 ,  H04L49/309 ,  H04L49/351 ,  H04L49/352 ,  H04L49/45 ,  H04L49/555 ,  H04L49/606 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9047 ,  H04L49/9063 ,  H04L49/9073 ,  H04L49/9094 ,  H04L67/10 ,  H04L69/14 ,  H04L69/16 ,  H04L69/161 ,  H04L69/323 ,  H04L69/329 ,  H04Q11/0478

摘要： A method and apparatus for optimizing access to memory, wherein the method includes the steps of receiving a first request for access to a memory, receiving at least two additional requests for access to the memory, and determining a first clock overhead associated with the first request for access to the memory. The method further includes the steps of determining an additional clock overhead associated with each of the at least two additional requests for access to the memory in conjunction with the first request, determining a combination of requests that can be processed together using an optimized overhead, and processing the combination of requests as a single request with the optimal overhead.