利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

20 条记录 (耗时 0.018 秒)

    InxGa1-xAsYP1-Y quaternary etch stop for improved chemical resistivity of gallium arsenide field effect transistors
    3.
    发明授权
    InxGa1-xAsYP1-Y quaternary etch stop for improved chemical resistivity of gallium arsenide field effect transistors 有权
    InxGa1-xAsYP1-Y四次蚀刻停止，用于提高砷化镓场效应晶体管的化学电阻率

    公开(公告)号：US08288253B1

    公开(公告)日：2012-10-16

    申请号：US13173006

    申请日：2011-06-30

    申请人： Allen W. Hanson ,  Anthony Kaleta

    发明人： Allen W. Hanson ,  Anthony Kaleta

    IPC分类号： H01L21/20 ,  H01L21/36

    CPC分类号： H01L21/30612 ,  H01L29/201 ,  H01L29/66462

    摘要： A process for fabricating a semiconductor device. The process including (a) growing a channel layer on a buffer layer, (b) growing a barrier layer on the channel layer, (c) epitaxially growing a quaternary etch-stop layer on the barrier layer, (d) growing a first contact layer on the quaternary etch-stop layer, (e) growing a second contact layer on the first contact layer, (f) etching portions of the second contact layer to reveal a first recess surface, and (g) etching portions of the first contact layer to reveal a second recess surface. The second contact layer may be a highly doped contact layer. The second recess surface generally forms a gate region. The first and the second contact layers have a first etch rate and the quaternary etch-stop layer has a second etch rate in a chosen first etch chemistry.

    摘要翻译： 一种制造半导体器件的工艺。 该方法包括（a）在缓冲层上生长通道层，（b）在沟道层上生长阻挡层，（c）在阻挡层上外延生长四分之一蚀刻停止层，（d）生长第一接触 （e）在第一接触层上生长第二接触层，（f）蚀刻第二接触层的部分以露出第一凹部表面，以及（g）蚀刻第一接触部分 层以露出第二凹槽表面。 第二接触层可以是高度掺杂的接触层。 第二凹面通常形成栅极区域。 第一和第二接触层具有第一蚀刻速率，并且四次蚀刻停止层在所选择的第一蚀刻化学中具有第二蚀刻速率。

    Process for selective recess etching of epitaxial field effect transistors with a novel etch-stop layer
    6.
    发明授权
    Process for selective recess etching of epitaxial field effect transistors with a novel etch-stop layer 失效
    用新颖的蚀刻停止层对外延场效应晶体管进行选择性凹陷蚀刻的工艺

    公开(公告)号：US6060402A

    公开(公告)日：2000-05-09

    申请号：US121160

    申请日：1998-07-23

    申请人： Allen W. Hanson

    发明人： Allen W. Hanson

    IPC分类号： H01L21/306 ,  H01L21/335 ,  H01L21/00

    CPC分类号： H01L29/66462 ,  H01L21/30612

    摘要： A process for selective recess etching of GaAs field-effect transistors. A selected etch stop layer (In.sub.x Ga.sub.1-x P) maintains what is commonly referred to as lattice-match with the GaAs substrate material. By using this etch stop, a significant reduction in access resistances is realized with respect to devices containing other etch stop materials while an improvement in the uniformity of device characteristics across the wafer and from wafer to wafer is realized.

    摘要翻译： 用于选择性凹陷蚀刻GaAs场效应晶体管的工艺。 所选择的蚀刻停止层（In x Ga 1-x P）保持通常称为与GaAs衬底材料的晶格匹配。 通过使用该蚀刻停止件，相对于含有其它蚀刻停止材料的器件实现了访问电阻的显着降低，同时实现了跨晶片和从晶片到晶片的器件特性的均匀性的改善。

    Gallium nitride material devices including conductive regions
    8.
    发明授权
    Gallium nitride material devices including conductive regions 有权
    包括导电区域的氮化镓材料器件

    公开(公告)号：US08067786B2

    公开(公告)日：2011-11-29

    申请号：US12508891

    申请日：2009-07-24

    申请人： Robert J. Therrien ,  Jerry W. Johnson ,  Allen W. Hanson

    发明人： Robert J. Therrien ,  Jerry W. Johnson ,  Allen W. Hanson

    IPC分类号： H01L33/00

    CPC分类号： H01L29/2003 ,  H01L23/481 ,  H01L24/89 ,  H01L29/78 ,  H01L29/78681 ,  H01L29/872 ,  H01L33/32 ,  H01L33/382 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/351 ,  H01L2933/0016 ,  H01L2924/00

    摘要： Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.

    摘要翻译： 提供包括III族氮化物（例如氮化镓）材料区域的半导体结构和与这种结构相关的方法。 在一些实施例中，结构包括由阻挡材料与结构的某些其它区域（例如，硅衬底）分离的导电材料（例如，金），以便限制或防止不希望的反应 导电材料和可能损害器件性能的其他部件。 在某些实施例中，导电材料可以形成在通孔中。 例如，通孔可以从装置的顶部延伸到背面，使得导电材料将顶侧触点连接到背侧触点。 本文所述的结构可以形成包括晶体管（例如FET），肖特基二极管，发光二极管和激光二极管等的多个半导体器件的基础。